h6. » [[OS SWI Calls|OS]] h6(. » [[OS_MMUControl]] h6((. » [[OS_MMUControl 2]] h6(((. » DSB_Read ARMop h2. DSB_Read ARMop |_<^{width:4em}. Entry | | |<^. - |<^. - | |_<^{width:4em}. Exit | | |<^. R0 |<^. Corrupt | h4. Use * Read barrier - writes may cross the instruction * Instructions following the barrier will only begin execution once the barrier is passed - but any prefetched instructions are not flushed from the pipeline h4. Notes There is no direct equivalent to this in ARMv7 (barriers are either W or RW). However it's useful to define a read barrier, as (e.g.) on Cortex-A9 a RW barrier would require draining the write buffer of the external PL310 cache, while a R barrier can simply be an ordinary DSB instruction. h4. See also * [[OS_MMUControl 2]]