h6. [[Hardware Abstraction Layer]] h6(. [[HAL entry points from RISC OS]] h6((. » HAL_IRQProperties h2. HAL_IRQProperties h5. (HAL entry #53) <pre> __value_in_regs struct { int irq, fiq; } HAL_IRQProperties(int device) </pre> |_<. Entry | | |device |Interrupt device number | |_<. Exit | | |irq |IRQ properties | |fiq |FIQ properties | h4. Use This is an internal call for OS use only and should not be used by user software. Returns information about the behaviour of the given interrupt. The low 16 bits of @irq@ and @fiq@ are bit masks, indicating which core(s) the interrupt can be routed to, and whether it can be routed as an IRQ or FIQ. E.g. a binary value of 11 for @irq@ indicates that the interrupt can be routed as an IRQ to either core 0 or core 1. The high 16 bits of @irq@ and @fiq@ provide extra flags: * Bit 31 is set if the interrupt can be assigned to multiple cores at once, clear if it can be assigned to (a maximum of) one core at a time. * Bit 30 is set if [[HAL_IRQEnable]]/[[HAL_IRQDisable]] (or FIQ equivalents) will only operate correctly if they are called from a core which the interrupt is currently routed to (e.g. private peripheral interrupts in a GIC). If the bit is clear, the calls will operate from any core, and the interrupt enable state is shared between all cores (e.g. shared peripheral interrupts in a GIC). * Bits 16-29 are reserved and should be zero. h4. See also * [[HAL_IRQSetCores]] * [[HAL_IRQGetCores]] h6. Information source: Kernel.Docs.SMP.IRQ in git