Showing changes from revision #2 to #3:
Added | Removed | Changed
Entry | |
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R0 | 0 + flags (reserved) |
Exit | |
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R0 | Flags |
R1 | Pointer to interrupt trigger routine (if bit 1 of R0 is set on exit) |
The purpose of this call is to return what is required to run code on the current hardware platform. The returned flags are influenced by both the properties of theCPU and the properties of the OS.
A New StrongARM flags platform are will added to the return bits value 0 in – R0 4 in set. a backwards-compatible manner. Therefore, on machines where thisSWI isn’t implemented (versions of RISC OS prior to 3.7) your code should act as if all the flags are set to zero. This can be done, for example, by checking if the SWI returns an unknown SWI error (error number &10F).
ARM 6 and 7 will return bits 0 – 4 clear.
Earlier machines will raise an error due to the SWI not being implemented. For such a machine, all the flags would be zero.
The routine returned in R1 is used to help trigger interrupts on CPUs where pending interrupts won’t be triggered as soon as the I bit is cleared. Enable interrupts and then call the routine to ensure that any pending interrupts have been processed. The routine is sutiable for calling from any CPU mode, and preserves all flags and registers, and is reentrant.