h6. » [[OS SWI Calls|OS]] h6(. » [[OS_MMUControl]] h6((. » [[OS_MMUControl 2]] h6(((. » DMB_Read ARMop h2. DMB_Read ARMop |_<^{width:4em}. Entry | | |<^. - |<^. - | |_<^{width:4em}. Exit | | |<^. R0 |<^. Corrupt | h4. Use * Ensures in-order operation of data load instructions * Does not stall instruction execution * Does not guarantee that any preceeding memory operations complete in a timely manner (or at all) h4. Notes Although this call doesn't guarantee that any memory operation completes, it's usually all that's required when interacting with hardware devices which use memory-mapped IO. E.g. after reading a hardware register to detect that a DMA write to RAM has completed, issue a read barrier to ensure that any reads from the data buffer see the final data. There is no direct equivalent to this in ARMv7 (barriers are either W or RW). However it's useful to define a read barrier, as (e.g.) on Cortex-A9 a RW barrier would require draining the write buffer of the external PL310 cache, while a R barrier can simply be an ordinary DMB instruction. h4. See also * [[OS_MMUControl 2]]