h6. » [[OS SWI Calls|OS]] h6(. » [[OS_MMUControl]] h6((. » [[OS_MMUControl 2]] h6(((. » DSB_ReadWrite ARMop h2. DSB_ReadWrite ARMop |_<^{width:4em}. Entry | | |<^. - |<^. - | |_<^{width:4em}. Exit | | |<^. R0 |<^. Corrupt | h4. Use This call is roughly equivalent to the ARMv7 "DSB SY" instruction: * Writebuffers are drained * Full read/write barrier - no data load/store will cross the instruction * Instructions following the barrier will only begin execution once the barrier is passed - but any prefetched instructions are not flushed from the pipeline h4. Notes Although ARMv7 has DSB and DMB instructions which perform write buffer drain-style operations in a cache-agnostic manner, these instructions do not operate on caches which are not fully integrated with the CPU - e.g. the PL310 L2 cache that's typically used on Cortex-A9 systems. Therefore, to ensure bufferable data is fully flushed to main memory, the memory barrier ARMops must be used rather than a direct ARMv7 sync instruction. This ARMop was previously known as WriteBuffer_Drain. h4. See also * [[OS_MMUControl 2]]