h6. [[Hardware Abstraction Layer]] h6(. [[HAL entry points from RISC OS]] h6((. » HAL_NVMemoryType h2. HAL_NVMemoryType h5. (HAL entry #23) <pre> unsigned int HAL_NVMemoryType(void) </pre> |_<. Entry | | |- | | |_<. Exit | | |/4^. Bits 0-7 |0 => no NVMemory available | |1 => NVMemory may be available on IIC bus | |2 => NVMemory is available on the IIC bus, and the device characteristics are known | |3 => the HAL provides NVMemory access calls | |Bit 8 |NVMemory has a protected region at the end | |Bit 9 |Protected region is software deprotectable | |Bit 10 |Memory locations 0-15 are readable | |Bit 11 |Memory locations 0-15 are writeable | h4. Use This is an internal call for OS use only and should not be used by user software. If bits 0-7 are 0 or 1 no other NVMemory calls need be available, and bits 8-31 should be zero. If bits 0-7 are 2, [[HAL_NVMemorySize]], [[HAL_NVMemoryPageSize]], [[HAL_NVMemoryProtectedSize]], [[HAL_NVMemoryProtection]] and [[HAL_NVMemoryIICAddress]] calls must be available. If bits 0-7 are 3, all calls except [[HAL_NVMemoryIICAddress]] must be available. Note that if the OS is using IIC to talk to the NVMemory (i.e. bits 0-7 are 1 or 2) then only IIC bus 0 can be used for the location of NVMemory. h4. See also * [[HAL NVRAM API]] h6. Information sources: Kernel.Docs.HAL.HAL_API, Kernel.s.PMF.i2cutils, HAL.Tungsten.s.NVMemory in CVS