h6. [[Hardware Abstraction Layer]] h6(. [[HAL entry points from RISC OS]] h6((. » HAL_VideoSetDAG h2. HAL_VideoSetDAG h5. (HAL entry #47) <pre> void HAL_VideoSetDAG(uint DAG, uint paddr) </pre> |_<. Entry | | |/5^. DAG |0 = Set start address of current video display | |1 = Set start address of total video buffer | |2 = Set end address (exclusive) of total video buffer | |3 = Set start address of VDU buffer (i.e. as set by [[OS_Byte 112|OS_Byte 112]]) | |All other values reserved | |paddr |Physical address for given DAG | |_<. Exit | | |- | | h4. Use This is an internal call for OS use only and should not be used by user software. User software should use [[GraphicsV]] instead of interacting with the HAL directly. The OS has a video buffer which is >= total display size, and may be using bank switching (several display buffers) or hardware scroll within the total video buffer. * DAG=1 will be start address of current total video buffer * DAG=2 will be end address (exclusive) of current total video buffer * DAG=0 will be start address in buffer for current display HALs should respond differently depending on whether hardware scroll is supported or not. (The OS will already know this from HAL_VideoFeatures). h5. No hardware scroll Only DAG=0 is significant, and the end address of the current display is implied by the size of the current mode. Calls with DAG=1,2 should be ignored. h5. Hardware scroll DAG=0 again defines display start. DAG=2 defines the last address (exclusive) that should be displayed before wrapping back (if reached within display size), and DAG=1 defines the address to which accesses should wrap back. h4. See also * [[HAL Video API]] h6. Information source: Kernel.Docs.HAL.HAL_API in CVS