h6. [[PCI]] h6(. » [[PCI SWI Calls|SWI Calls]] h6((. » PCI_RAMAlloc h2. PCI_RAMAlloc h5. (SWI &50390) |_<^{width:4em}. Entry | | |<^. R0 |<^. Size required | |<^. R1 |<^. Alignment required (e.g. &1000 it must be 4K aligned - 0 if none) | |<^. R2 |<^. Boundary limitation (e.g. &10000 it mustn't cross 64K boundary - 0 if none) | |_<^{width:4em}. Exit | | |<^. R0 |<^. Logical address| |<^. R1 |<^. Physical address| |<^. R2 |<^. Preserved| h4. Use The purpose of this call is to allocate memory from a fixed, contiguous memory pool, suitable for access by other bus masters. h4. Notes This is provided for the convenience of drivers that only need a few simple data structures for communication with their PCI device, and don't want the complexity of dealing with cache coherency, memory fragmentation and physical page moving ([[Service_PagesUnsafe]] et al). Memory will be uncachable but bufferable - you must ensure that any writes you perform have taken place before another bus master reads the memory, e.g. by using the barrier routines available through [[OS_MMUControl 2]], or by calling [[OS_MMUControl 1]] with bit 28 of R0 set. The memory is not accessible from user mode. h4. See also * [[OS_MMUControl 1]] * [[OS_MMUControl 2]] * [[Service_PagesUnsafe]]