h6. [[Hardware Abstraction Layer]] h6(. » [[RISC OS entry points from HAL]] h6((. » RISCOS_Start h2. RISCOS_Start h5. (OS entry #2) <pre> void RISCOS_Start(unsigned int flags, int *riscos_header, int *hal_descriptor, void *ref) </pre> |_<. Entry | | |/5^. flags |Bit 0: power on reset | |Bit 1: CMOS reset inhibited (eg protection link on Risc PC) | |Bit 2: perform a CMOS reset (if bit 1 clear and bit 0 set - eg front panel button held down on an NC) | |Bit 3: there is no CMOS (the Kernel must use a RAM cache) | |Bit 4: the RAM has already been cleared to zero | |riscos_header |Pointer to "OS image header":HAL%20OS%20layout%20and%20headers#osim | |hal_descriptor |Pointer to "HAL descriptor":HAL%20OS%20layout%20and%20headers#haldescriptor | |/4^. ref |Reference value that was returned by the last call to [[RISCOS_AddRAM]] | |SVC32 mode | |MMU and data caches off | |IRQs and FIQs disabled | |_<. Exit | | |- |This call does not return| h4. Use This routine must be called after all calls to [[RISCOS_AddRAM]] have been completed. It does not return. Future calls back to the HAL are via the HAL entry table, after the MMU has been enabled. h6. Information sources: Kernel.Docs.HAL.HAL_API, Kernel.hdr.OSEntries in CVS