Armv9 announced

Arm has announced Armv9. Most of this is over my head, but I figured it’s still worth a mention! Plenty of buzzwords in there :)

AArch32 support is listed as “EL0 only”.

https://www.arm.com/campaigns/arm-vision
https://www.theregister.com/2021/03/30/arm_v9_chips/

300 billion, huh?

That works out to be about 42 for every single human on the planet.

Holy s**t.

42.

ARM was the question.
42 was the answer.

We’ve got it!

Reality will now kill -9

Oops.

“EL0 only”

For those two don’t speak ARMese, it’s back to front to Intel and the typical idea of protection rings. Execution Level 0 is the least privileged mode.

So what this means is “AArch32 still exists, but only in USR mode”.

Which means 300 billion chips that won’t run RISC OS as it stands. Hmm… Didn’t we have a long thread about this? :-p

Aarch32 might be specified as EL0 only in ARMv9, but I’ll guarantee it will never feature in an ARMv9 application (Ax) processor. It will be retained as a backwards compatibility option for some micro controller (Mx) and real time (Rx) cores.

Agreed with David.

it makes no sense for the Ax processor when even Linux 64 runs better than Linux 32, and for Linux on ARM “every little helps”.

However, if (in the remote case) that there might be some CPUs having an AArch32 in EL0 then that would help to run old RO 5 Apps without binary translation to AArch64 or recompiling them.

Remember it is the 31st of March

Nothing seems particularly outlandish with this announcement, except for the continual references to Artificial Intelligence which is anything but…

I find the SVE/SVE2 thingy quite interesting, quote from Anandtech:

" SVE2 was announced back in April 2019 , and looked to solve this issue by complementing the new scalable SIMD instruction set with the needed instructions to serve more varied DSP-like workloads that currently still use NEON.

The benefit of SVE and SVE2 beyond addition various modern SIMD capabilities is in their variable vector size, ranging from 128b to 2048b, allowing variable 128b granularity of vectors, irrespective of what the actual hardware is running on. Purely from a view of vector processing and programming, it means that a software developer would only ever have to compile his code once, and if in the future a CPU would come out with say native 512b SIMD execution pipelines, the code would be able to already take advantage of the full width of the units."

Here’s also a direkt link to a presentation about SVE2: SVE2 Presentation

There are two main approaches to running (classic) RISC OS on such a chip. One requires emulation, the other requires magic unicorns.

How many magic unicorns?

It depends on how many horns they have.

I can find plenty of unicorns with two horns, other people call them deer. I think you are thinking of multihorns but I haven’t seen any.

Every unicorn has two horns. Every unicorn has thirteen horns. Both these statements are true. A universally quantified predicate on the empty set is necessarily true.

To the best of my knowledge and belief, there are two species of unicorn on Earth, one of them with at least two sub-species. How many species of unicorn there are elsewhere in the universe is beyond my ken; your guess is as bad as mine.

Are all multiples of 11 between 2 and 7 equal to 4 modulo 11? Yes, because that’s unequivocally the empty set. Unicorns? Rhinoceroses & narwhals, arguably; who knows what else within a radius of 14 billion lightyears?

</argumentative mode>

That works out to be about 42 for every single human on the planet.

Rather more, I think. But I have to admit to not knowing what percentage of humans are single.

</flippant mode>

<pedantMode>

Rhinoceroses & narwhals

Two species of rhino have one horn, while three have two (those that still have horns, that is…). But on the other hand, their horn is actually made of entirely of keratin, so I’m not sure it counts as a horns. The narwhal horn, meanwhile, is a tooth with illusions of grandeur, so that seems even more suspicious!

</pedantMode>

Indeed, I was aware that only some rhino species have one horn, and that teeth and rhino horns are only arguably horns – hence “arguably” in my post…

</defensiveMode>

<apologeticMode>

I missed the word “arguably” – sorry! ;)

</apologeticMode>

But I have to admit to not knowing what percentage of humans are single

Dunno, but I think 42 is a factor in the division required to count the ones with intelligence.
Although recent evidence from the USA suggests I may be missing a few zeros required to make the output smaller.

@ Rick

Nothing seems particularly outlandish with this announcement, except for the continual references to Artificial Intelligence which is anything but…

Well AI/ML is fuelling pretty much everything right now in the IT, Security, Home, IoT, Embedded market (and every other aspects of Computer Science). So ARM had to address it loudly to gather even more interest. Even PCie5 is being pushed toward providing special protocols to improve AI/ML, so literally everything that can be used for AI/ML is now receiving interest.

ARMv9 so far seems to be a great architecture, but only time will tell. Most likely next Apple big thing will be already on ARMv9 (they had the architecture definition by long time already). So maybe M1X will be ARMv9 or maybe M2 will be.

It’s interesting the huge development of the Hypervisor, the Realms should allow (in theory) almost complete isolation of a guest or an App. If that is true then we (as ARM developers Linux etc., not RISC OS) could start moving some features that now is forced to be in the Secure OS to the Realms and that would make things easier and maybe even faster (but I am speculating on the perf side).

What all this means for RISC OS? Right now not much. The usual song, to even think (in the future) to get advantage of any of the new ARM stuff RO 5 needs to be converted to C. If people wants to use Emulation then there is no need to look at ARM, we already have RPCEmu and that is what RO emulation is.

@ Kuemmel

I find the SVE/SVE2 thingy quite interesting

Oh yes, very exciting what they are promising there, will see how it plays out, but yeah I like it a lot too :)

The Realms are also a very interesting concept that captured my attention.

Best part of the presentation? When they showed a diagram where to indicate the traditional PC approach they used a picture of an Amiga 2000!!!!!! :D (brilliant detail! lol)

Realms is aimed at cloud service providers, giving similar protection to AMD’s SEV, expect to see it in AWS’s Graviton 3.

I take it from the partial retention of ARM32 support that the RISC OS devs are far from the only ones wrestling with a huge codebase of legacy assembler.

Realms is aimed at cloud service providers, giving similar protection to AMD’s SEV, expect to see it in AWS’s Graviton 3.

Yup, ARM themselves use Graviton for their cloud assets, but I think Realms are also potentially great for general virtualization. I am thinking of ThunderX as well as what will come next from Qualcomm as well as a perfect feature for OSes like Qubes… :)

I take it from the partial retention of ARM32 support that the RISC OS devs are far from the only ones wrestling with a huge codebase of legacy assembler.

I think it’s mainly so Arm can claim to be providing backwards compatibility. In reality, I think most SoC implementations won’t bother paying extra to license that (and waste space on the die) so you’ll struggle to find an Armv9 chip that includes AArch32 at all.