SWP and Other Instructions Added To ACE for compatibility

ACE (ARM Chip Emulator) adds instructions to your computer to make it more compatible with the different processors available. It should work on all versions of Risc OS 5.

SWP, SWPB, UDIV, SDIV, MOVW, MOVT, CLZ, BFC, BFI, SBFX, UBFX are all emulated by this software if your hardware cannot run the instruction.

Some of these instructions are missing off many machines. SWP from some Raspberry Pis and all the others from the Risc PC and therefore RPCEmu.

For those wanting to add their own instructions there is some SWIs that allow you to do this without most of the hard work. You will need to be able to write your own modules. The SWI range is in the user range at the moment as I have not applied for an official SWI block. Ideally it would also have a service call for start/end but this is not implemented.

One example of an added instruction is included in BASIC that makes a module. This instruction takes two registers and counts the number of bits set in one register, storing the result in the destination register.

There are a couple of * commands that I forgot to add to the help files. *ACEHandlers and *ACEHandlersBinary. Both of these show the handlers that are active at the time.

The source code for the main module is not included as it is complete mess with lots of testing code built in that needs to be removed but I may provide it at a future time when it is a bit cleaner.

This is available at http://www.ro32.co.uk

@ Graeme

This is really cool, great job so far! :)

I have discovered a bug in my software. It affects Raspberry Pi users and others using later hardware. It does not affect Risc PC or RPCEmu.

I’ll update here when the bug has been fixed.

ACE Bug Fixed.

The bug has been fixed and you should be able to download version 0.04 now.

It affected the SWP instruction when it was conditional. The instruction was being run even if the condition was not met. This is now fixed and I believe working correctly.

got release 004 fine, thanks!

Well done :-)

I wonder if a similar idea couldn’t be used in replacing the Fpu module on machine’s with floating point hardware?

I have added a few new instructions to ACE, now version 0.05. There are some bug fixes too including the divide commands that could cause an address exception on occasion or round incorrectly compared to how Raspberry Pi would round. This now emulates the following instructions:

SWP, SWPB
UDIV, SDIV
MOVW, MOVT
CLZ BFC, BFI, UBFX, SBFX
SADD16, SASX, SSAX, SSUB16, SADD8, SSUB8, QADD16, QASX, QSAX, QSUB16, QADD8, SHADD16, SHASX, SHSAX, SHSUB16, SHADD8, SHSUB8, UADD16, UADD8, USUB8, UQADD16, UQASX, UQAX, USQSUB16, UQADD8, UQSUB8, UHADD16, UHASX, UHSAX, UHSUB16, UHADD8, UHSUB8, SSAT16, USAT16, SSAT, USAT, QADD, QSUB, QDADD, QDSUB, SEL, PKHBT, PKHTB
SXTAB16, SXTB16, SXTAB, SXTB, SXTAH, SXTH, UXTAB16, UXTB16, UXTAB, UXTB, UXTAH, UXTH, USAD8, USADA8
REV, REV16, RBIT, REVSH
SMLAD, SMLADX, SMLSD, SMLSDX, SMUAD, SMUADX, SMUSD, SMUXDX, SMLALD, SMLALDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR
SMULBB, SMULBT, SMULTB, SMULTT, SMLABB, SMLABT, SMLATB, SMLATT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLAWB, SMULWB, SMLUWT, SMULWT

This time they have been stress tested, running through hundreds of thousands of results that have been saved on real hardware and then tested against the emulation.

Note that some instructions set the Q or GE flags in the CPSR. The flags will not be set on some hardware (or RPCEmu) due to the fact that those flags are hardwired to be zero at all times. The maths to the instruction will still work. I have added a few instructions where you can read or set these flags where you can replace MSR or MRS if absolutely needed.

@Paolo, thanks. Glad you appreciate it. Please make sure you have version 0.05 to fix two UDIV/SDIV bugs.

@Colin, this module definitely could replace the FPE with VFP. I am not convinced that there would be much time saved. In fact, with the overhead of my module it could potentially be slower than the currently available efficient FPE.

@ Graeme

Glad you appreciate it.

I think it’s really cool and reminds me of the 68060.lib I use on the Amiga to emulate the missing 68K instructions on the 68060, so I think your work has a lot of potentials.

Please make sure you have version 0.05 to fix two UDIV/SDIV bugs.

downloaded, thanks a lot!

ACE (Arm Chip Emulator) now has the source code in the download. This module adds instructions to your computer including SWP, division, parallel maths and more.

ARMChipEmulator (ACE) is now version 0.06 and has a simple update to emulate BX and BLX instructions along with many more.

If you get the dreaded “Undefined Instruction” error on a program you are trying to run, try loading in the ACE module first and it may be that those instructions can be emulated for you. Potentially giving you a working program.

These instructions are only emulated if your processor does not have them.

For programmers:

BX and BLX instructions that jump to an address held in a register will work. The versions of the instructions that jump to a defined address cannot be emulated and are therefore not supported.

Further, jumping to a register value where the address attempts to switch mode (changing from 32-bit mode to 16-bit Thumb mode) will also fail with an undefined instruction error.

This emulates the important instruction BX PC,LR (or BX PC,R14) that seems to be a common method of returning from a function.