Norcroft 64

Alternatively, modify RISC OS to use the generic timer instead, which is implemented.

I’m busy, but maybe asking nicely on a qemu forum would work?

It’s a core for a processor that is supposed to be sort of RISC, how the hell does that alone get to eight and a half thousand pages?

Requirements have evolved, processors need to help with more intensive and specialized stuff. So, you now have VFPE, NEON, memory management, crypto, IA, etc. And since if come in 32-bit and 64-bit versions, that doubles the size.

It’s a core for a processor that is supposed to be sort of RISC, how the hell does that alone get to eight and a half thousand pages?

There is a lot of duplication and each instruction seems to take at least two pages to describe. Various formats are shown (32-bit, 64-bit and a number of thumb sets). Every instruction has an algorithm to show what it does which takes up space.

When I say every instruction, I mean it. STMFD and STMFA are two different instructions in this manual. The older manuals had a couple of pages for MOV/MVN/ADD/SUB/MUL and all the bitwise operations. Now ADD and ADDS are listed separately with each taking a couple of pages.

There are a huge number of instructions now. ADD can have U, S, Q or SH in front of them and 8 or 16 on the end in most combinations. There are pushing 50 versions of LDR and STR (like LDR, LDRB, LDRH, LDREX and more). That is a lot of two pages when each is classed as separate. I guess it is for the algorithms to be simpler.

As a side note, does anybody know what language those algorithms are in? Are they available from ARM as a text file because they would be very useful to make an emulator.

That is a lot of two pages when each is classed as separate. I guess it is for the algorithms to be simpler.

That may be the reason, or maybe the author was paid by the word/page.

The v8 ARM ARM is autogenerated from (I think) an XML spec. It is more important that it is correct, accurate and complete than it being concise or particularly readable.

As a side note, does anybody know what language those algorithms are in?

If you refer to pseudo code like the following:

MBReqDomain domain; 

MBReqTypes types; 

case CRm<3:2> of

    when ‘00’ domain = MBReqDomain_OuterShareable; when ‘01’ domain = MBReqDomain_Nonshareable; when ‘10’ domain = MBReqDomain_InnerShareable; when ‘11’ domain = MBReqDomain_FullSystem;

case CRm<1:0> of

    when ‘00’ types = MBReqTypes_All; domain = MBReqDomain_FullSystem; when ‘01’ types = MBReqTypes_Reads;

    when ‘10’ types = MBReqTypes_Writes;

    when ‘11’ types = MBReqTypes_All;

This is a non standard pseudo language used to describe how the CPU decode or process each instruction. In other words it’s not a “programming language” per se, but it can be translated into one. I use a similar approach to design the software components for my UltimaVM. Given that when you optimize code a lot, many people won’t be able to understand what the code is actually doing.

Are they available from ARM as a text file because they would be very useful to make an emulator.

Yes, some of the pseudo code examples should be also on the on-line version of the Arch Ref Manual. But the PDF one is top notch, because you can click on each internal register “type” which contains the structural definition, so I find it way more useful.

On the “to make an emulator”, we have Sarah here one of the most talented developer I have seen on the matter of writing emulators, so I am sure she will have a ton to say. In my personal experience on the matter, the pseudo code above is very useful to understand what the real CPU truly does behind the scenes, but the emulator code will need to take consideration of software optimizations, which the pseudocode doesn’t consider at all (and for obvious reasons).

In other words, the pseudo code should be seen as a very detailed description of what the real CPU will do functionally speaking in that specific situation, then it’s up to you how that same result has to be produced in ASM, C, C++, Java or Rust etc. in the best possible way for correctness and performance.

HTH

It is more important that it is correct, accurate and complete than it being concise or particularly readable.

indeed!

Reading about the Phebe RiscPc2 project on 4corn site – one difference quoted by Acorn was a increase in RAM from 512Mb to 1024Mb from the RiscPc.

Reading about the Phebe RiscPc2 project on 4corn site – one difference quoted by Acorn was a increase in RAM from 512Mb to 1024Mb from the RiscPc.

No, please read more carefully. The physical address space was increased to 1024MB. That is NOT the same as the amount of RAM. That would be akin to saying an A310 could have 64MB of memory because that was the size of its physical address space.

. DRAM (32or 64MB SDRAM as 2 DIMMs with expansion upto 512MBs)
. Video memory fixed at 4MB EDO VRAM

From https://www.4corn.co.uk/archive/Acorn_Developer_Site/docs/hardware/phoebe/funcspec.html

Seeing this thread I couldn’t help think "What if a dozen or so RISC OS programmers on the David Pilling level knowing both 32-bit Arm asm and modern C conspired on GitHub or such to do a 64-bit version of RISC OS using multi-threading and preemptive multitasking, maybe also multi-CPU/GPU, with full emulation of RISC OS 3.7 apps “built in”? It could open for production of blistering fast RISC OS computers, suitable for heavy GFX and audio creation and editing. That’d be nice.

Let’s all remember not to feed the troll.

I just knew somebody would say that, in the no-mans land between ruling brainless culture and The Stockholm Syndrome – a conditioned reflex. Good doggie.

Let’s all remember not to feed the troll.

Dave, given you’re the closest thing this forum has to a moderator, if you actually believe this, you could just ban them and save us all the aggravation.

Splendid idea.

Please, no ban. SWT isn’t offending anyone. His unrealistic dreaming is just ‘like a broken pencil’ (as Blackadder said).

Much as the idea appeals, it’s a bit like hanging – it’s a bit late to find the perpertrator was actually innocent, merely misguided/misunderstood. I suspect that Dave will want to keep his powers, much appreciated in their execution, low profile.

SWT isn’t offending anyone.

And Sargasso now has an exclusion facility if one wishes to use it. If only people would stop responding, the perceived problem would go away!

Sargasso?

Sargasso?

An RSS feed reader, M’lud, originated by James Bursa and fairly recently very-kindly retro-fitted with with a selective-kill facility by Chris Gransden from whose site the modified version is currently available.

This was added by request after a spate of imaginary experts challenged Rick, amongst others, for the title of “wordiest” contributor.

It was necessary because people will keep on feeding the trolls!

Presumably one that runs on RISCOS then? Ah, okay. Mostly I access this site from the Mac… heigh ho.

Presumably one that runs on RISCOS then?

I wonder how well it would handle a Mac usergroup feed. Do they have trolls there as well? I expect so.

I expect such a facility could be added to a Mac RSS feed reader if it were absent.

But nothing beats self-discipline and self-restraint, which is really the point I’m trying to make.

To make a personal witty response may be momentarily satisfying, but just prolongs the agony for many.

Do they have trolls there as well?

Dunno, I’m not on any Mac usergroups. I guess they probably have though.

To make a personal witty response may be momentarily satisfying, but just prolongs the agony for many.

Indeed. Apologies for the occasions I’ve been guilty.

for the title of “wordiest” contributor.

😋

In my first posting to this thread should be added “Pensioned RISC OS C/asm Programmers” – a glimmering opportunity to take advantage of new CPU/GPU features (realtime raytracing!) and maybe turn the current trend of rapidly disappearing RISC OS users. They’d be true heros.

Just had a look at http://www.codemist.co.uk/index.html , the makers of the Norcroft C compiler system. Although Acorn/RISC OS stuff is a very small part of their former business projects their former directors appear to be available for queries.

I’m thinking, could any of their compiler tools/support systems not sold off, or still being commercial products be used to aid in a RISC OS 32-to 64-bit conversion? It’s a long shot, both the job itself and matters of (32-bit) RISC OS compability, but it wouldn’t hurt to ask.