RISC OS IA-32!
Rick Murray (539) 13806 posts |
It is known that x86 instructions are microcoded. It is also known that the microcode is interpreted by a fast RISC processor. What is not generally known is that the RISC core is actually a variant ARM processor. Following Intel’s development work for the XScale processor, it was realised that the ARM core was substantially suitable for running at high speeds to work as the back end of x86 architecture CISC processing units. Now, thanks to the Chinese company “Bèndàn Èzuòjù Group” (a company that essentially specialises in chip-stripping and cloning), they have uncovered a way to switch out of x86 mode and in to ARM mode. A specially constructed data table needs to be created, and ES:EDI set to point to it. There are several caveats – all interrupts (software or hardware, and vectors (abort, etc)) will automatically switch the processor back to x86 mode. Only one core can be used at a time – the x86 translator works for all cores however the state of the processor (ARM or x86) is only available to the core that is set to handle the interrupt/vector. The other cores will change state as the translator is re-enabled for all cores with no notification. This eccentricity of design precludes the ability to use multiple cores in ARM mode. The handlers for the interrupt and vector conditions will then need to deal with the issue (as an x86) and then switch back to ARM mode. It is not currently believed to be possible to create a reentrant handler that switches to ARM mode immediately, as the x86 does not appear to switch to x86 mode while it believes it is in the handler. The necessity to switch back and forth does cause a lag, but on a 2.6GHz processor, the speed is judged to be “acceptable” (about as fast as a RaspberryPi), however the actual speed depends upon the number of interrupts – USB transfers (especially USB networking) really hammers it. Expect networking in this manner to be slow. There may also be issues with missing or repeated keypresses, though these are expected to be ironed out in time due to further developments of the x86 handlers. For those with a suitable x86 32 system (sorry, the specifics of the IA64 core are not currently known), a bootable CD image of RISC OS 5.19 may be downloaded from http://www.riscos-ia32.cn/ and I expect the (somewhat old) version of RISC OS to be updated in the following weeks. |
Malcolm Hussain-Gambles (1596) 811 posts |
You lot are no fun! |
Steve Pampling (1551) 8155 posts |
ah youth. The tradition is for pre-12 noon shipment of such missives otherwise they are returned to sender. I suppose it is pre-noon in Hawaii. |
Bryn Evans (2091) 31 posts |
The tradition is that you land your “Peche” before Noon! |
patric aristide (434) 418 posts |
The company also trades under the following name on alibaba IIRC: |
John Williams (567) 768 posts |
Rick – the poisson d’avril finishes at midday! Fish pie for you tonight! |
Rick Murray (539) 13806 posts |
As a non-morning person (and having gone to work this morning anyway) I tend to ignore the noon rule1. :-) 1 Which I feel was instigated by a British2 person with no sense of humour so they could get back to their scheduled boredom. |
Chris Evans (457) 1614 posts |
A bit late in the day but one of the best I’ve seen today:-) |
GavinWraith (26) 1563 posts |
Just like Des Cartes, who did not like to rise before 3 o’clock in the afternoon. I suppose you have all seen Riscository’s ( http://www.riscository.com/ ) Breaking news? |
Rick Murray (539) 13806 posts |
Yeah, well, you’re laughing now. We were all laughing, once. Spooks were like Mulder, right? Then this bloke called Snowden came along… |
Steve Pampling (1551) 8155 posts |
There has to be rules. |