SWP Instruction and Emulation

I am looking at emulating the SWP instruction in a module.

I guess LDREX, STREX would be an appropriate substitute?

For processors that do not have these LDREX/STREX instructions, would turning off interrupts and fast interrupts be enough to emulate this (they will be a single processor) or would I be better to fail to complete the instruction?

If you’re hooking into the Undefined instruction vector on a unicore and FIQ isn’t in the equation, an STR/LDR with a DMB should suffice as IRQ will already be disabled when UND32 is entered.

The helpfile of PatchSWP will give you a lot of useful information.

www.tellima.nl/riscos/

Thanks. I think I have this working.

So far, I am checking OS_PlatformFeatures to see if LDREX or LDREXB are available. If they are, I am using the spinlock from that helpfile, if not then DMB instructions are being used instead.

I didn’t realise that SWP also causes cache synchronisation so I’ve added that too. I may release the module soon for people to test the instructions added. At the moment there is UDIV/SDIV, SWP/SWPB and CLZ.

UDIV/SDIV and CLZ could be useful on RPCEmu/RiscPCs and SWP/SWPB on Raspberry Pis.

Good news :)