OS_MMUControl 1 bit 29
Jon Abbott (1421) 2651 posts |
The Wiki entry for OS_MMUControl 1 states “Bit 29 is currently ignored. Future versions may correct.” with reference to flushing a single cache entry. Is this still the case or has it now been implemented? |
Jeffrey Lee (213) 6048 posts |
It’s still ignored. If we were to implement it, we’d probably also want to add support for doing a ranged flush. |
Jon Abbott (1421) 2651 posts |
Could it be added easily? It’s the only bit I’m missing that’s preventing me switching all JIT cache ops to RISCOS SWI’s. We also need to allow you to specify if it’s the I / D or both that need flushing. |
Jon Abbott (1421) 2651 posts |
It doesn’t look like ranged TLB flushing is exposed either. How about extending OS_MMUControl to provide these ARMOps via SWI? |