Does BASIC's assembler yet support LDRD/STRD instructions?

Hello,

I’ve been playing with Matt Godbolt’s excellent ‘Compiler Explorer’ (https://godbolt.org/), and I successfully compiled a fixed-point-math cubic Bézier curve calculator for inclusion with a cross-platform (x86/ARM) project. The ARM code generated by GCC 5.4.1 worked as intended (although I didn’t at first notice the more recent version – 4.6.3 – was available and which produces somewhat more efficient code). However, I noticed when I used the following compiler switch,

-O2 -march=‘armv6’ -marm

two handy instructions I hadn’t seen before, LDRD and STRD (load & store doubleword) were generated, and they shaved off 9 instructions from the code. My code uses ‘long long’ (64-bit) integers, which is why these instructions were generated.

Does BASIC’s assembler support those two instructions yet? I tried using them under RISC OS 5.21, (ARM BBC BASIC assembled 24 Sep 2014) on my Raspberry Pi 2 and also under RPCEmu, but no joy. If the latest version of BASIC does support LDRD/STRD, then I’ll upgrade without delay.

I found the encodings for them from

http://qcd.phys.cmu.edu/QCDcluster/intel/vtune/reference/INST_LDRD.htm

so I suppose I could write a macro to implement the instructions myself, although I feel this may be more involved than at first glance (not tried this sort of thing before!).

David.
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5.23 supports LDRD. If you type “HELP [” in BASIC, it will list which instructions it understands.

Thank you Jon, somehow I had forgotten about the “HELP [” command!

Having just downloaded an old edition of the ‘ARM ARM’, I was on the verge this evening of ‘hand-assembling’ LDRD/STRD myself, so I’m pleased I won’t now have to do that.

Happily, those instructions are supported by BASIC’s assembler in RISC OS 5.22, which is what I’ve been using with RPCEmu.

David.
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Is it possible that the version of LDRD/STRD with an offset (e.g. LDRD R3,[R11,#8]) is not yet supported by the Assembler ?…I get an error (“bad register”) when trying to assemble this…I’m using Risc OS 5.23.

LDRD R3,[R11,#8]

R3 isn’t a valid initial register, it has to start with an even register. Is that the cause of the error?

…I’ll check in the evening. Are you sure it’s not allowed ?

On page 39 of ARM’s optimisation guide for Cortex A57 the example uses R3 (other Syntax: LDRD R3,R4,[R1,#0]). Find the link to the document here

Maybe that’s a bug in the ARM documentation if it’s not allowed ?

I guess that sample code was written under the assumption you’d be writing Thumb code.

The Thumb version of LDRD allows Rt and Rt2 (the two destination registers) to be any two registers apart from (A) R13 and R15, (B) they can’t both be the same, and © if writeback is enabled they can’t be Rn.

The ARM version is restricted to Rt being even and Rt2 being Rt+1. You can’t use R15, and there’s the same restriction as the Thumb version regarding writeback.

My ARM ARM of ARMv7 vintage states:

The pair of registers is restricted to being an even-numbered register and the odd-numbered register that immediately follows it (for example, R10 and R11).

If you look at the encoding you’ll see there’s a very good reason for that!

I looked at my code again, as you all said, the problem was the R3, so even-numbered is a must. Thanks for the hint ! Even if obvious now while also looking at the latest ARM ARM I think I’ll write them a mail to clarify that example…

By the way, there’s also a similar guide to the Cortex A72, you can find here

It’s quite an interesting read in comparison with the A57, as you can see some evolution (of course a reduction) in instruction latencies, especially floating point like VMUL, VADD, but also integer UDIV/SDIV. A similar document for A15 doesn’t exist, so they seem to be more open on that now…a further one for the A73 will be prepared also.