ARMv7 NEON instruction encodings

I can find huge swathes of technical information, tutorials and user manuals concerning the (ARMv7-A/R) NEON instruction set, but I can’t find any online reference material containing the actual NEON instruction binary encodings (needed to add NEON instruction support to an assembler). I believe I’ve had a good look! Can anyone provide a link to an online reference that includes the binary encodings?

You want the ARMv7 ARM

Or really the ARMv8 ARM, since ARMv8 does introduce a few new instructions for AArch32.

You do need to register to download them, but I think it’s a relatively painless experience nowadays.

Thanks very much, Jeffrey. I could swear I’d already downloaded the ARMv7-A-R PDF document, but yet somehow managed to miss what I was looking for.

ARMv8 does introduce a few new instructions for AArch32

Ooh, I must take a look see what they are. ARMv8 proper I took at look at and thunk, “I don’t think I’ll bother,” but any changes to ARrch32? Could be interesting…for a rather specific sort of nerd…

https://www.element14.com/community/servlet/JiveServlet/previewBody/41836-102-1-229511/ARM.Reference_Manual.pdf

Starts on page 106.

This doc comes at a good time, as I am starting to try to accelerate some KinoAmp stuff by using NEON variants of some routines and I have a few questions:

First, which -CPU value to use to get rid of the “Instruction not supported on targeted CPU” ?

Also, I was trying to check if VFP presence meant NEON presence and looking at system register MVFR0 (via VFPSupport_Features 0), the bottom 4 bits values define the number of 64-bit registers for NEON, which can be: 0, 16 or 32.

So NEON may not be present or could also be restricted to registers d0-d15 (q0-q7) instead of the d0-d31 (q0-q15) that is commonly used in code on the net. So my second question: Do some RISC OS ported machines use this presumably old 16 registers variant or can I freely make use of the 32 registers?

First, which -CPU value to use to get rid of the “Instruction not supported on targeted CPU” ?

Cortex-A8 should be fine.

So my second question: Do some RISC OS ported machines use this presumably old 16 registers variant or can I freely make use of the 32 registers?

NEON guarantees 32 doubleword registers. Section A2.6.2 of the ARMv7 ARM contains a summary of how many registers are allowed to be present for each VFP/NEON combination. The only machine we support which has 16 doubleword registers is the Pi 1 (ARMv6, VFPv2, no NEON).