Apple's M1

@Colin: Pretty much what Rick said…I’m currently diving into that by playing with some small examples written on Linux AArch64.

A nice overview from ARM is this presentation. Check page 31ff …your new friend for conditional execution is called “CSEL”…not much left of the old times in that respect…but it keeps my brain from becoming too ‘rusty’, if you can say that in english…

A nice overview from ARM is this presentation.

Obviously, more registers means more bits required to encode them in instructions so its no wonder that they had to drop conditional execution. Anyway, I never have enough registers when trying to optimize routines in assembler so I think it’s a good tradeoff.

Looking at this document, you can still use branch table but you need 3 instructions ADR, ADD, BR.

The most curious part is the alignment requirements of SP. I would have understood 8-bytes since it uses 64-bit registers but 16-bytes ?

The most curious part is the alignment requirements of SP. I would have understood 8-bytes since it uses 64-bit registers but 16-bytes ?

The FP/SIMD registers are 128 bits wide, and need to be stored at their natural alignment on the stack.

ARM – the original instruction set, was designed by a human for humans. It’s very elegant and allows for very optimal code, that’s easy to read/follow.

I expect AARCH64 was vicariously designed by a C compiler, where conditional instructions are just an unnecessary complication. I know that if I were designing a modern CPU instruction set, I’d base it heavily on statistical analysis of the target OS’s codebase.

How about an AARCH64 version of the OS gets called RISCish OS?

I don’t really care what it’s called, but if it gets done I shall be Very Impressed Indeed.

If it’s got functional !Draw, !Zap, and BBC BASIC I shall be even impresseder!

How about an AARCH64 version of the OS gets called RISCish OS?

I vote for “Arthur 2” ;-)

I vote for “Arthur 2” ;-)

Shouldn’t that be “Arthur 3”? But it gets complicated since “Arthur” is “RISC OS 1”…so RISC OS 3 would already be Arthur 3, we’re now on Arthur 5, and Arthur SIX is already taken, so probably “Arthur 7”?

I would suggest “RISC OS Reloaded” instead. Then we already know what we call the 128bit variant: “RISC OS Revolution” :-)

I would suggest “RISC OS Reloaded” instead. Then we already know what we call the 128bit variant: “RISC OS Revolution” :-)

RISC OS Insurrection :)

As the ISA is no longer similar to what we are familiar with.

To put it VERY mildly!

so not sure what the relation is.

Can’t believe you’ve never seen The Matrix. Add that to your bucket list (but only The Matrix, the two sequels are optional and very Marmite ¹).

Steve is likely referring to one of the Star Trek movies. And I will take it in a different direction by suggesting:

RISC OS Salvation ;-)

¹ It’s a British yeast extract gloop with a pungent odour and matching taste that a lot of people spread on toast for some reason. It is also notorious for nobody being “meh” about Marmite. You either love it or hate it, with no in between. The Aussie version is called Vegemite.
And what I’m basically saying is that people either love or hate the sequels.

Can’t believe you’ve never seen The Matrix.

I know that wasn’t addressed to me, but I for one have never seen The Matrix.

I’ve seen Blade Runner, and Easy Rider, and A Passage to India. Oh, and Tommy the Toreador, The Court Jester, South Pacific, and Oklahoma – the last four when I was just a little kid.

How about “I Can’t Believe It’s Not RISC OS”?

Can I suggest porting RISC OS to the Maxim MaxQ?

It shouldn’t be too hard, this processor only has one instruction.

https://www.maximintegrated.com/en/design/technical-documents/app-notes/3/3222.html

Darned pop culture references

I heard about the Beatles some time in the 60s. I have even heard the Rolling Stones, once at the Sussex University summer ball, before they were famous, and once at a concert in Aarhus. My daughters gave me a tape to play in the car when I was on the school run: Crowded House, Jethro Tull et al. Apart from that I am totally ignorant of popular music. I have not been to a cinema for thirty years, because I always found the sound-volume actually painful. I wonder how often cinemas are prosecuted for for breaking public health by-laws on sound-levels? Besides, who needs cinemas when there is YouTube where you can set your own sound levels, and not have to wade through other people’s popcorn.

I’ve seen Blade Runner, and Easy Rider, and A Passage to India.

Snap. Not seen the others, though. My impression is that there is too much action in a lot of modern films. You can hardly tell whether you are watching human beings or frenetic cartoon characters. Just compare Mizoguchi’s The 47 Ronin (1941), how superior it is to later remakes.

Steve is likely referring to one of the Star Trek movies.

Two for the price of one (STNG and Jan 6th).
Subconscious thing I think – we have CAB¹ meeting each Tuesday and I had put a large proportion² of items in.

¹ Change Authorisation Board, for items that have, or could have, a significant impact.

For the original definition of RISC, I would direct people to the Reduced instruction set computer architecture IEEE publication. As with Moore’s Law, it’s been somewhat corrupted over the years.

I vote for “Arthur 2” ;-)

…On the rocks?

I notice that Sophie Wilson prefers the definition of RISC as Reduced Instruction Set Complexity.

I notice that Sophie Wilson prefers the definition of RISC as Reduced Instruction Set Complexity.

IMHO this is actually the modern correct definition of the RISC acronym.

For the original definition of RISC, I would direct people to the Reduced instruction set computer architecture IEEE publication.

Good old Stalling paper, yes, but I’d like to mention that things have evolved quite a bit and modern architectures presents specialised cores, not just GP cores, such specialized cores can also be designed with a RISC philosophy in mind and that is what the M1 really is. Apple has done their homework well.

As with Moore’s Law, it’s been somewhat corrupted over the years.

True and reviewed multiple times already. While the other general laws in the field of Microprocessors design which are the Denard scaling ended around 2004 and Amdhal’s law still govern the parallelisation of processes and in modern computing it’s vital for the prescription of practical limits to the number of useful cores per chip.

But again looking to an architecture simply from an ISA point of view in modern computing is just blindly looking at the problem, there has been such an advancement in CPU design that the General ISA it’s just part of the architecture.

there has been such an advancement in CPU design that the General ISA it’s just part of the architecture.

Quite. Most, if not all mass produced CPU’s are RISC at core; the number of instructions is now academic.

Most, if not all mass produced CPU’s are RISC at core;

Stuff out of Intel allegedly has ARM in there in a number of cases and where it isn’t ARM it’s a home-grown equivalent.

I get the impression that it is a VLIW CPU at the core of most Intel x86 CPUs since P6 to present.

Oh the true x86 architecture died many years ago.
I believe it’s been more efficient core with glue logic to pretend to be x86 style for many a year.

The ARM bit is from an article I read the other month. I forget the specific chip, but it struck me as ironic to be using a competitor design at the core of your own. It sort of says “we lost”

People discovered the Intel Management Engine (the processor to manage the processor) runs Minix.
It’s not very clear what CPU they used in the past
- it seems to be called an embedded micro-controller and a RISC core.
It would have been fun if the X86 had a fast 32 bit ARM hidden inside it; if it did we could discover the secret bypass instruction for all the clumsy X86 instructions; and run RISC OS on all our Pentiums.

CPUs these days are like the TARDIS; many more registers on the inside.

I don’t think it is ARM inside the x86, but it is a RISC core.

It sort of says “we lost”

I’m not so sure it’s a case of “we lost” so much as “FFS, how much longer are we going to have to support this god-awful architecture?”.

I wonder if it wasn’t for Windows, if x86 would have been ditched about the time the 68000 stopped being popular?

I mean, think about the raw brute force that the Intel RISC core must have to translate x86 instructions, execute them, and still wipe the floor with most of the competition? Imagine if they ditched the x86 crap and made the RISC core native. Whoo-ee, that would be a fast beast. Might not even need a heatsink the size of a tower block either!