Prodding Cthulhu

It’s amazing what sort of information you can extract from a modern ARM processor…though I’m not entirely sure why most of this stuff uses four bits per item when a bitfield would suffice…

CPU ID is &410FB767.
Implementor  : &41 (ARM Ltd)
Variant      : &00
Architecture : &F (Revised CPUID - see below)
Primary part : &B76 (&B = 11, so CPU is 1176)
Revision     : &7

Extended CPU information is available:

State 0 (32bit ARM)         : Supported
State 1 (Thumb-1)           : Supported
State 1 (Thumb-2)           : Not supported
State 2 (Jazelle)           : Supported
State 3 (ThumbEE/JazelleRCT): Not supported (Thumb/Jazelle depends on core)

ARMv4 programmer's model    : Supported
TrustZone security          : Supported
Microcontroller prgrmr model: Not supported

Core debug coprocessor      : Supported
Secure debug coprocessor    : Supported
Core debug memory mapped    : Not supported
Trace debug coprocessor     : Not supported
Trace debug memory mapped   : Not supported

VMSA (v7)                   : Supported
PMSA                        : Not supported
Cache coherence             : Not supported
Outer shareable             : Not supported
TCM                         : Supported
Auxiliary Control           : Supported
FCSE                        : Supported

L1 cache maint. MVA/Harvard : Supported
L1 cache maint. MVA/unified : Not supported
L1 maint. Set/Way MVA/Hrvrd : Supported
L1 maint. Set/Way MVA/unif. : Not supported
L1 all maint. Harvard       : Supported
L1 all maint. unified       : Not supported
Data cache test/clean       : Not supported
Need flush br.pred on VAchng: Yes

Foregnd prefetch cache range: Not supported
Backgnd prefetch cache range: Not supported
Cache maintenance range     : Supported
TLB maintenance, Harvard    : Supported
TLB maintenance, unified    : Supported
Memory barrier operations   : Supported
Wait For Interrupt stalling : Supported
Hardware access flag        : Not supported

Hierarch cache maint MVA    : Not supported
Hierarch cache maint Set/Way: Not supported
Branch predictor maintenance: Not supported
Support for supersections   : Not supported

SWP and SWPB (atomic ld/str): Supported
CLZ (bit counting)          : Supported
Bitfield instructions       : Not supported
Compare-and-branch instrs.  : Not supported
Co-processor instructions   : Supported (always reads as 0 on Cortex-Axx)
Debug (BKPT) instruction    : Supported
Divide instructions         : Not supported

Endiannes control SETEND/E  : Supported
Excep#1 LDM(2)/LDM(3)/STM(2): Supported
Excep#2 SRS/RFE/CPS         : Supported
Sign/zero extend instructs  : Supported
IfThen instructions         : Not supported
Immediate instructions      : Not supported
Interworking instructions   : Supported
Jazelle instructions        : Supported

LDRD and STRD (ld/str dble) : Supported
PLD (preload)               : Supported
Restartable LDM and STM     : Supported
Multiply: MUL, MLA, and MLS : Supported
Signed multiply: SMULL etc  : Supported
Unsigned multiply: UMULL etc: Supported
PSR (MRS and MSR)           : Supported
Reversal instructions       : Supported

Saturate instructions       : Supported
SIMD instructions           : Supported
SVC instruction             : Supported
Synch primitive instructions: Supported
Table branch instructions   : Not supported
Thumb copy instructions     : Supported
True NOP instructions       : Supported
Thumb-2 ENTERX/LEAVEX instrs: Not supported

Unprivileged LDR{SB|B|SH|H}T: Supported
With-shift instructions     : Supported
Write-back addressing modes : Supported
SMC instruction             : Supported
Barrier instrs (DMB/DSB/ISB): Not supported
Exclusive / Sync. Primitive : Supported