PCI_MemoryRead/Write with more than 1 word

While prodding (metaphorically) a PCI parallel port card I came across some odd behaviour with these two SWIs which I thought would be an easier route since a parallel port only has a couple of registers.

It seems that

• For PCI_MemoryRead the PCI memory address is fixed at one location, and the RAM buffer is filled up with N repeated reads of that same location. That in itself seems a bit pointless, given it’s a PCI memory region, but I’ll ignore that for now.
• For PCI_MemoryWrite the source buffer address is constant and the PCI memory address is incremented, ie. it’s basically a memset() operation.

A quick search of the ROOL source tree shows they’re never used, for example EtherK just maps in the memory region with PCI_HardwareAddress and peeks/pokes that logical copy.

For the write case, since OS_Memory 14 (and 15) are used, the maximum memory window is 1MB after which you’ll get a data abort. Of course, for access sizes of 4 (like PCI_IORead and PCIIOWrite) the behaviour is quite natural – you ask for 4 bytes and get 4 bytes.

I think the post increment for PCI_MemoryWrite should be on the RAM buffer address, not the PCI address, at least then it’d be symmetrical with respect to PCI_MemoryRead, and not data abort if you want to send more than a meg. Does that seem reasonable?

While prodding (metaphorically) a PCI parallel port card

If it’s of any interest, I have a module (PCIParallel, two actually as it calls the pport stuff from PCISerial), that implements the ParallelOp SWIs.
This worked from a sunix PCI serial card that had a pport on-board. If you want it, you can have the source. I used the same PCI_HardwareAddress method to access the registers.

Tank