RISCOS Hypervisor

Seeing the mention of a Hypervisor in the Linux port thread has reminded me to re-raise this project, which is to build a type 2 Hypervisor to host IOC / IOMD VM’s.

Of the four issues I originally highlighted, two (Page Zero relocation and Cache flushing) have been resolved and one partially resolved (Memory switching) by RISCOS changes. Although a Timer API would be required for an accurate (IOC/IOMD) timer emulation, I found a partial workaround in calculating the flyback time in timer ticks and then raising a virtual IRQ at the end of each scanline within the blitter if T0/T1 is triggered. This is sufficient to get one VM that uses T0/T1 to work but wouldn’t work if multiple VM’s used timers, as it relies on blitting the frame buffer at 50hz. Another drawback is that it can’t emulate the IR pin¹ correctly, so code that relies on accurate FLYBK don’t work².

A possible workaround to emulate T0/T1 across multiple VM’s is to do a fake raster scan of all VM’s that aren’t visible. T3/T4 are set to sufficiently low speeds to hardcode emulate via RTSupport, if you ignore the ability to reprogram them.

A lot of changes have gone in around memory switching, but there’s still the issue of no public means to switch tasks and switching memory ranges outside of the taskswitcher’s normal range, such as 0-8000 and the ROM image area.

¹ FLYBK. VIDC brings the IOC IR pin high during flyback and low during display. The state of the IR pin can be read via Bit 7 of the IOC Control Register

² I’m aware of two games that use FLYBK – the original 1990 releases of Tactic (Eterna) and Ballarena (Eterna)