spinrw and register naming conventions
André Timmermans (100) 655 posts |
I noticed the usage of multiple register naming conventions in the code of spinrw updated last night in the CVS.
Would it not be clearer to stick to a single naming convention? |
Chris Hall (132) 3554 posts |
Don’t understand. R0 and R1 are named and R0 is preserved during the call. |
Jeffrey Lee (213) 6048 posts |
I think the problem is that no matter what register naming scheme you use, you’re going to have to do some mental conversion between the different schemes. If you write the code using just APCS register names, you’ll have to mentally translate between APCS and ARM when writing or reading code that makes SWI calls or interfaces with other native RISC OS APIs. One advantage of using the right scheme in the right place is that the scheme can imply that certain conventions are used – e.g. if you’re reading code that uses APCS register names, you can be fairly certain that the code is APCS compliant (so any function calls are expected to clobber a1-a4 & ip). If you see ARM register names then all bets are off (some components will be nice and preserve all registers, other routines are nasty and will clobber lots of them without warning – the kernel seems pretty notorious for this) There’s also a historical problem that there used to be many APCS variants (with different register mappings), so if you were writing APCS code then using APCS register names was the only option you had.
He’s talking about APCS register names (a1-a4, v1-v6, etc.) vs. ARM register names (R0-R15/PC) |
Rick Murray (539) 13840 posts |
Which given one starts with zero and the other starts with one, twice, is annoying. I “solved” this by simply remembering the APCS requirements, as much as I needed to, and then writing code using exclusively the native register naming scheme. You’ll also note, by the way, that various SWI call mechanisms use native register assignments and not APCS. So I consider APCS to be “optional”. ;-) |