Norcroft unsigned long long brokenness

Behold:

#include <stdio.h>
#include <stdlib.h>

#if 1
typedef unsigned long long u64;
typedef unsigned int u32;
#else
typedef signed long long u64;
typedef signed int u32;
#endif

u32 sys_clk = 13000000;

void calculate_dss_clock_divider(u32 pixel_rate)
{
    pixel_rate = pixel_rate*2;
    u32 regm=1;
    u32 regn=7;
    u64 dsiphy64=(((u64)sys_clk)*((u64)2)*((u64)regm))/((u64)regn);
    u32 regm3=(u32) (dsiphy64/((u64)pixel_rate));
    printf("64: regm=%d regm3=%d dsiphy=%d\n",regm,regm3-1,(int)(dsiphy64));
    u32 dsiphy32=(sys_clk*2*regm)/regn;
    regm3=(u32) (dsiphy32/((u64)pixel_rate));
    printf("32: regm=%d regm3=%d dsiphy=%d\n",regm,regm3-1,(int)(dsiphy32));
}

int main(int argc,char **argv)
{
    calculate_dss_clock_divider(25175000);
    return 0;
}

*cc test.c
Norcroft RISC OS ARM C vsn 5.65 [18 Apr 2006] (Jeffrey_Lee)
*test
64: regm=1 regm3=553634 dsiphy=1230847798
32: regm=1 regm3=-1 dsiphy=3714285

*cc test.c
Norcroft RISC OS ARM C vsn 5.65 [18 Apr 2006] (Jeffrey_Lee)
*test
64: regm=1 regm3=-1 dsiphy=3714285
32: regm=1 regm3=-1 dsiphy=3714285

Stuff also seems to break if you mix the signed & unsigned types (signed long long, unsigned int). I don’t have enough time at the moment to narrow down the precise bits are broken, but needless to say I’m not happy :( (This is running Norcroft with default settings after a clean boot, btw)

Also, if the suspect code is in the SCL: My Iyonix is running 5.54, but my BeagleBoard (which is where I first found the bug) is obviously running the latest – 5.56

Looks like the optimiser is unhelpfully optimising out a register initialisation.

One workaround would be to disable the peepholer: pass -zpq8 to cc or, perhaps more usefully, surround the function with #pragma -q8 … #pragma -q0. Obviously, this option has both code size and speed implications. It does, however, appear to make the above code produce the correct output with unsigned arithmetic.

I have confirmed that if any divides are done everything starts working by the way. So yes.. looks like optimiser.

try this.

#include <stdio.h>
#include <stdlib.h>

#if 1
typedef unsigned long long u64;
typedef unsigned int u32;
#else
typedef signed long long u64;
typedef signed int u32;
#endif

u32 sys_clk = 13000000;

void calculate_dss_clock_divider(u32 pixel_rate)
{
  // workaround
  u64 moo = 1000;
  moo /= 2;
  // end workaround
  pixel_rate = pixel_rate*2;
  u32 regm=1;
  u32 regn=7;
  u64 dsiphy64=(((u64)sys_clk)*((u64)2)*((u64)regm))/((u64)regn);
  u32 regm3=(u32) (dsiphy64/((u64)pixel_rate));
  printf("64: regm=%d regm3=%d dsiphy=%d\n",regm,regm3-1,(int)(dsiphy64));
  u32 dsiphy32=(sys_clk*2*regm)/regn;
  regm3=(u32) (dsiphy32/((u64)pixel_rate));
  printf("32: regm=%d regm3=%d dsiphy=%d\n",regm,regm3-1,(int)(dsiphy32));
}

int main(int argc,char **argv)
{
  calculate_dss_clock_divider(25175000);
  return 0;
}