PlingSystem CLib using ARMv3 instructions
Jon Abbott (1421) 2651 posts |
Whilst debugging some issues I’m seeing with the PlingSystem CLib handling Callbacks and Stack unwinds on RO3.11, I’ve noticed some ARMv3 instructions within it: CallbackHandler Is the PlingSystem CLib supposed to work on ARM3? |
Chris Mahoney (1684) 2165 posts |
I believe that it’s supposed to work on every pre-OS5 system, so yes, it’s supposed to work on ARMv3. |
Rick Murray (539) 13850 posts |
Smoke and mirrors time. 1749: MRS r0, CPSR On ARM600 and later, we copy the CPSR into R0. 1750: TST r0, #2_11100 Here we test R0 AND %11100; and R0 will either be the CPSR or zero. ... We can skip this bit. 1762: ; if in a 26-bit mode - mark PSR in register dump as invalid. 1763: MOVEQ r12, #-1 1764: STREQ r12, [r11] And here we come to doing something with the result of the TST. In this case, it is a little back to front in that the EQ condition is used if the bits in TST were not set. So, if not in a 32 bit mode, or if on a system that doesn’t even support MSR/MSR, the Z flag will be set so the 26 bit behaviour will be invoked. It relies upon MRS/MSR doing nothing at all on the original ARM processors. |
Jon Abbott (1421) 2651 posts |
I believe its this that’s the root cause of the issues I’ve seen, not all emulators NOP TST without the S bit – which admittedly is a bug in the emulator. It just seems a little odd to me, to purposely include instructions that are going to be a NOP though, for the most part, occurrences of MSR/MRS within RISCOSLib are either conditional or wrapped in compiler conditions to exclude them on the ARM3 build. |
Rick Murray (539) 13850 posts |
Using MSR/MRS like that when written as explained above makes code that can work on any ARM. If there is no separate status register, the instruction is a NOP so does nothing. This can be used to our advantage. |
Martin Avison (27) 1494 posts |
I thought that TST is never NOPd? |
Stuart Swales (1481) 351 posts |
Indeed – any sane assembler applies an implicit S bit for TST and TEQ. |
Rick Murray (539) 13850 posts |
ARM instruction set document (from ARM7TDMI ref manual): The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented using the TEQ, TST, CMN, and CMP instructions without the S flag set. Thus, on the ARM2 and ARM3, it is quite likely that the processor sees one of those (TEQ-CMP) and actually executes it, but since the S flag is not set, the result is discarded. In other words, it behaves as a NOP. So, yes, any sane assembler would set the S bit for TST, TEQ, etc. However with it unset, it’s an entirely different instruction. |