compile with hardware float
Etienne SOBOLE (3572) 28 posts |
Hi. I’ve bench CC and GCC in order to see the quality of the produced code. I’ve realised the same test on A BSD server-3.3 Ghz XEON (only to check the difference). For Integer test, CC and GCC produce almost the same code quality and the RaspBerry Pi is 2 or 3 times slower than the XEON (it’s quite normal) My conclusion therefore is that GCC and CC do not use Hardware floating point operation under RISC OS ! Is there any way to do that ? thank’s |
Jeffrey Lee (213) 6048 posts |
CC only knows how to use the old FPA floating point instruction set, which means all floating point instructions will actually be emulated via the FPEmulator module (very slow). GCC supports FPA, softfloat, and VFP. IIRC FPA is the only option if you’re linking against the shared C library. Unixlib defaults to softlfloat (which is faster than FPEmulator). VFP must be specifically enabled, since it’s only supported by the newer CPUs:
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Etienne SOBOLE (3572) 28 posts |
Thank you Jeffrey for informations ! VPf is not very fast, -mfpu=neon improve the speed of factor 3.5 far far away from Intel float performance. It does not matter. I will just avoid using float :) |
Andrew Rawnsley (492) 1445 posts |
I’m not sure if it is still the case, but it is also worth remembering that the Pi isn’t the fastest VFP implementation. Certainly the numbers from the BASIC VFP thread were significantly lower that the (same-ball park clock-speed) i.MX6 system I tested on (basically Pi was roughly half the Titanium, and i.MX6 was closer to Titanium than to Pi). It has generally been a “rule of thumb” (pardon the bad pun) not to use float with RISC OS due to historical deficiencies and ARM CPUs being stronger with integer maths. Intel CPUs, by contast, have always been floating point kings (it tended to be an area of strength over their rivals at AMD, even when the wind wasn’t blowing in their direction in other areas). As such, you’re probably looking at the weakest part of the Pi, and comparing to the strongest aspect of the Xeon. |