Thumb-2 code working on Risc OS - Usefullness beyond sizecoding ?

As one might have overlooked it in the announcement section, recently while digging into tiny intro sizecoding on Risc OS again we found out that basically Risc OS can run Thumb-2 code without any problem (at least tested on RPi3 and RPI4 by now), what was kind of a surprise. It was there since a long time, kind of untouched :-) Even SWI’s calls are working (tested a few SWI numbers 0×00 – 0xff, others have to be called by OS_CallASWI). In Thumb-2 mode you can use also still use all other ARM instructions including Neon/VFP.

I just wonder in general if that’s of any usefullness beyond size coding for Risc OS. When I google about Thumb-2 there isn’t much about it, of course it’s all about code size reduction in the embedded sector, and those Cortex-M SOC’s seem to run only in Thumb-2 mode. Regarding speed, since Thumb-2, there doesn’t seem to be a penalty. I guess since we got all that extra memory, reducing code size isn’t a factor, or is it somewhere in the OS itself ?

For sizecoders it’s a huge playground…offering quite weird instructions like If-Then, table branch…I guess also C code could generate Thumb-2 code…

I think this might be useful for javascript, because the webkit JS engine (JIT) is optimised for ARMv7 with thumb extensions now (I believe) rather than just vanilla ARMv7. The question is how to enable that so it plays nice with the toolchain and RISC OS environment…

Sure, for people that want to make their code even less future proof, esoteric and hard to reverse engineer. Too good to be true, right?