3200000 Base of IOC registers

This number seems to have stayed the same for sometime – but with RO5 it changed.
Is there a SWI available to give this new address? RO4 and above.

Have a module that wants to do this.
**********

SWI OS_ReadMonotonicTime ; it’s been read too, only changes a1(?)
STR r0,[v1] ; Store cs part r0=a1 reg
MOV a3,#&03200000 ; Base of IOC registers
STRB r0,[a3,#&4C] ; Transfer T0 count to &40,&44
LDRB a2,[a3,#&40] ; Read T0 count low
LDRB a1,[a3,#&44] ; Read T0 count high
************

A HAL call?

If not – it’s a bit of a hack but maybe you could extrapolate from the Parallel_HardwareAddress call where the machine thinks the I/O is (assuming I/O is largely mapped together so moving IOC-timer-stuff will also affect the combi-I/O chip address).

If you really want to get the base of IOC/IOMD under RISC OS 5, I believe the correct way is via OS_Memory 9, requesting controller type 4 (i.e. set R1 to &400). ROL chose a different number to use, so for RISC OS 4+ you’d need to request controller type 33 (i.e. set R1 to &2100). That might only work on Select and above though.

Of course the above solutions will only work on IOMD hardware, a proper solution for getting a high frequency timer value would (for RISC OS 5) involve using OS_Hardware 0 to call the HAL counter API. For Select, you’d want to use the Timer module

If you’re writing code that needs to use timers I recommend Rik Griffin’s HALTimer module(s). See http://squeakysoftware.org/haltimer.html and http://www.riscosopen.org/forum/forums/4/topics/1600 for a discussion about using it.

Is the HALTimer module supposed to work with RO5/RPC? – I get an error here when I try and run it. RO5.19 (05 Mar 13)