How to run bare metal code under RISC OS?

I have downloaded two ARM machine code IMG files from github, written by Peter Lemon as Julia and Mandelbrot set demos. The question is: can I run them from within RISC OS without crashing everything? They both program the GPU for output. The Mandelbrot code ends with an instruction to branch to itself!

The question is: can I run them from within RISC OS without crashing everything?

That all depends on how bare metal they are.

Do they run with the MMU on or off?
What are they doing to the GPU?
Is there any other hardware they talk to?

The Mandelbrot code is only 444 bytes. The first instruction that is new to me is reported by StrongED as VMSR FPEXC,R0. Then there is stuff which I am guessing is setting up the GPU to use a 640×480 mode:
MOV R1,#640
VMOV S31,R1
VCVT.F32 S32 S0,S31
VMOV.F32 S2,S0
followed by more instructions with Vs and S operands. I am guessing that these all do things with the GPU. There are some VMRS APSR_nzcv,FPSCR instructions which I think test for flyback and bottom-of-screen. Finally there is an instruction to branch back to the same instruction, so presumably switching off is the only way out.

Is this sufficient to answer your questions? There is stuff at the beginning with CP15, which I think is to get the other cores contributing. Can anybody give pointers to readable documentation?

I was looking at his ReadMe Page here

I think that all of that code run’s directly on the firmware (so no chance for RISC OS directly)…so no “real” high level operating system or how you would call that (no knowledge about that basic firmware, may be something like a command line OS)…but somehow also very interesting !

He also got a multicore Julia code, might be a good read for how to do multicore support, it’s here

VMOV, VCVT, etc. are VFP/NEON instructions. They’re nothing to do with the GPU.

The armasm docs seem to have pretty good documentation for them.

There is stuff at the beginning with CP15, which I think is to get the other cores contributing.

That looks like it’s enabling the caches & VFP/NEON unit.

Can anybody give pointers to readable documentation?

Funnily enough if you look at the source code you’ll see that there are plenty of comments ;-)

https://github.com/PeterLemon/RaspberryPi/blob/master/NEON/Fractal/Julia/kernel7.asm

If you ripped out the core computation code and converted it to a RISC OS friendly format (BASIC, ExtASM, objasm and asasm should all be able to handle the required VFP/NEON instructions) then it shouldn’t be too hard to get the code running on RISC OS. However he seems to favour the pre-UAL syntax (fmuls, etc.) rather than the UAL syntax (vmul, etc.) – so depending on what assembler you use you might need to translate to UAL to get it working (Other than the ARM ARM I’m not really sure of a good reference for how to convert from pre-UAL to UAL syntax. But there is at least a basic reference here in the Cortex-A8 TRM)

You’ll need to use the VFPSupport SWIs to create a VFP/NEON context, rather than using CP15 ops to enable it manually. Kuemmel has a few VFP/NEON examples showing this, or there’s my own metaballs demo