Footnotes
3 posts, 1 voice
Trevor Johnson (329)
1645 posts
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1 test <code><RiscPkg$@@Apps.Admin.!RiscPkg></code> @<RiscPkg$@@Apps.Admin.!RiscPkg> no pre here @<RiscPkg$@@Apps.Admin.!RiscPkg> no pre here 1a 1b @<RiscPkg$@@Apps.Admin.!RiscPkg> 2 <pre><code></code>@<RiscPkg$@@Apps.Admin.!RiscPkg></pre> 2a <RiscPkg$@@Apps.Admin.!RiscPkg> 3 <pre><RiscPkg$@@Apps.Admin.!RiscPkg></pre> 4 @<RiscPkg$@@Apps.Admin.!RiscPkg> 5 <RiscPkg$@@Apps.Admin.!RiscPkg> 6 <RiscPkg$@@Apps.Admin.!RiscPkg> 7
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14 <RiscPkg$@Apps.Admin.!RiscPkg> 15 <RiscPkg$@Apps Admin.!RiscPkg> 16 <RiscPkg$@Apps.Admin.!RiscPkg> 17 <RiscPkg$@==Apps.Admin.!RiscPkg> See foo1. See foo2 (test) …encourage the wider community to experiment with RISC OS3. …encourage the wider community to experiment with RISC os4. …encourage RISC OS experimentation by the wider community5.
1 Foo. 2 Foo with space and no full stop. 3 Why doesn’t this work? Substituting 4 Lower case seems OK! 5 “Rephrase this sentence…” – aargh! 6 Note that there’s currently a bug that will cause RAM disc creation to fail. As a workaround, the BASIC program listed here is run to disable alignment exceptions before trying to create the RAM disc. (This file is also saved to disk. You’ll probably wan’t to keep it for future use as required by some programs at the moment.) |
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Trevor Johnson (329)
1645 posts
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https://www.riscosopen.org/content/downloads/cvs-access :pserver:<code></code>@anonymous@@riscosopen.org:/home/rool/cvsroot Colin’s suggestion :pserver:anonymous::@riscosopen.org:/home/rool/cvsroot CVS manual (pg20) [:method:][[user][:password]@]hostname[:[port]]/path/to/repository https://www.riscosopen.org/wiki/documentation/pages/OS+SWI+Calls https://www.riscosopen.org/wiki/documentation/pages/OS_FSControl blah10 Inline image test (apparently broken) . . . I have never formatted anything let alone a memory stick, so what settings should I use?Choose ‘A’ (no more changes) when it asks you about adding entries to the defect list. Otherwise, the default settings should work just fine. |
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Trevor Johnson (329)
1645 posts
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<pre>struct PixelBlock gives struct PixelBlock
{
int pixel4;
};
PixelBlock *spriteRow;
PixelBlock *screenRow;
void f(PixelBlock *spriteRow,PixelBlock *screenRow)
{
for(int i=0; i!=10; ++i)
{
PixelBlock sprite=spriteRow[i];
PixelBlock screen=screenRow[i];
screen.pixel0|=sprite.pixel0;
screen.pixel1|=sprite.pixel1;
screen.pixel2|=sprite.pixel2;
screen.pixel3|=sprite.pixel3;
screenRow[i]=screen;
}
}
int main()
{
f(spriteRow,screenRow);
}
YMMV
; R12 -> sprite data
; R11 -> frame buffer
; R9 = number of pixels (words, not bytes) to plot
; r7 = translucency value (alpha = 0 to 255)
plot_bit_translucent
RSB r6,r7,#&ff ; 1 - alpha
CMP r9,#0
trans_loop
BEQ bit_finished
LDR r0,[r11] ; frame buffer pixel
LDR r1,[r12],#4 ; source pixel
AND r2,r0,#&ff ; frame buffer red component
AND r3,r1,#&ff ; source red component
MUL r3,r7,r3 ; src * alpha
MLA r5,r6,r2,r3 ; + back * (1 – alpha)
AND r5,r5,#&ff00
; r5 is red component << 8
AND r2,r0,#&ff00 ; back green << 8
AND r3,r1,#&ff00 ; src green << 8
MUL r3,r7,r3 ; src * alpha
MLA r4,r6,r2,r3 ; + back * (1 – alpha)
AND r4,r4,#&ff0000
; r4 is green component << 16
AND r2,r0,#&ff0000 ; back blue << 16
AND r3,r1,#&ff0000 ; src blue << 16
MUL r3,r7,r3 ; src * alpha
MLA r3,r6,r2,r3 ; + back * (1 – alpha)
AND r3,r3,#&ff000000
; r3 is blue component << 24
MOV r5,r5,LSR#8 ; combine the 3 components
ORR r5,r5,r4,LSR#8 ; into the correct bytes of r5
ORR r5,r5,r3,LSR#8
STR r5,[r11],#4
SUBS r9,r9,#1
B trans_loop
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