How riscy is the ARM? (off topic)

I am entertaining the idea of programming
a raspberry pi in assembler/machine code
as a preparation for compiler-work.

I found good literature on the subject on
the internet, but could not help noticing
that no author mentions the complications
RISC is notorious for: exposure of the
CPU pipeline to machine code programmers.

On the MIPS CPU, for example, you cannot
use the target register of an ALU op in
the very next instruction, because the
result has yet to travel through the pipeline.

No author mentions such traps for the ARM,
what is a pleasant surprise for me. So
here is my question for people in the know:

The ARM does NOT expose the pipeline to
machine code programmers — right? The ARM
is as fun and easy to program in assembler
as the 68000 (for example), right?

Thanks for your patience.

Generally speaking ARM CPUs will automatically detect and deal with pipeline hazards, so you don’t have to worry them yourself.

However there are a couple of exceptions:

• A couple of older CPUs had notable hardware bugs which could cause bad things to happen with certain code sequences (ARM2 TEQP bug, StrongARM conditional MSR bug). But if you’re only interested in the Pi then you shouldn’t have to worry about that.
• On newer CPUs explicit synchronisation instructions are needed for some operations (e.g. making sure a write to IO memory completes before the CPU re-enables interrupts). But you should only have to worry about that if you’re going to be writing low level code like device drivers.

It’s also worth pointing out that most ARM CPUs (including the Pi) don’t perform out-of-order execution – so if you’re interested in writing high performance assembler code then you might want to manually schedule some code sequences to avoid too many pipeline stalls.