RISC-V Chip

My mate just just tagged me in on this…

A new RISC-V opensource chip “This chip’s capabilities are almost on par with a low-power ARM Cortex M0”

Risc-V

http://hackaday.com/2016/11/22/mrisc-v-the-first-open-source-risc-v-microcontroller/

Interesting discussion in the comments…maybe they’ll get to the point of it being interesting eventually…

And the reason why this topic is in “Porting RISC OS” is because…?

And the reason why this topic is in “Porting RISC OS” is because…?

Probably because the OP thought (wrongly) that RISC and “almost on a par with a low power Cortex M0” meant that it actually had some kind of ARM component

We have already a better choice. A GPL ARM core.
Available on the Mist: https://www.dragonbox.de/en/285-mist-fpga-fpga.html

There is some RISC OS 3 compatibility. But it would be fun to tweak the core and the peripherals to get something more modern.
Under a possible port of RISC OS 5 of course.

Emulators could also follow the same path, to get RISC OS 5 compatibility.
When we’ll have both GPL hardware and RISC OS 5 in RISC OS 5 emulation.

I have no knowledge of FPGA. But I would certainly support any new work on Mist+ARM+RISCOS.

… or – let’s be crazy – a 26bit version of RISC OS 5.
Would be fantastic for emulators, virtualization, old computers, etc.

I have no knowledge of FPGA. But I would certainly support any new work on Mist+ARM+RISCOS.

I love my MIST, but I don’t think it is useful beyond the “simulate some classic computers” field. The Archimedes core already pushes the MIST FPGA to its limits (although its author thinks that he can speed it up quite a bit), so implementing an ARMv7 core instead of the current ARMv2a core is probably off-limit.

Of course there are much more powerful FPGAs available, but they get quite pricey quickly. And they would need to be perhaps 100x faster than the MIST’s FPGA to offer comparable speed to a 1 GHz Cortex-A9 or Cortex-A15.

First up – is this device even remotely ARM like? Or is it “yet another RISC microcontroller that reckons to make it big within a decade”?

Second up – 26 bit was. The necessary things don’t exist on modern ARM and need to be faked. Let’s leave it at that and look towards the future…

Probably because the OP thought (wrongly) that RISC

Not at all, I am more than understanding that RISC !== ARM however ARM == RISC…

however, I was interested, maybe Aldershot would have been better?

Still got people chatting…

Do we have to stick with ARM? (running and hiding after throwing a huge turd in the thread) :@P – No I was never seriously suggesting this as a option…

The phrase “Derivative Work” means any derivative work which is based on, or derived from, RISC OS or any part of RISC OS (whether by modification or translation) and any work subsequently derived from such Derivative Work or any part of it PROVIDED THAT such work is only intended to be used in conjunction with an embodiment (whether physical or emulated) of one or more versions of the ARM processor architecture.
https://www.riscosopen.org/tarballs/Licence_v1_1.pdf

That said, I’d like to see somebody attempt to port RISC OS to a different architecture. I mean, there are easier ways to experience pain and psychological trauma…

Also, implementing anything beyond ARMv2a or ARMv3 on a FPGA will wake up ARM’s “dogs of law” (pun), as more modern ARM architectures are heavyly guarded by patents and licences.

That said, I’d like to see somebody attempt to port RISC OS to a different architecture.

??? You want to see someone violate the terms of the licence? Or had David’s quote not appeared to remind you when you posted.

Funny question: Would a hypothetical pure AArch64 processor, i.e. one without the AArch32 part, still be covered by the licence? From a technical point of view AArch64 is as alien as any other processor, in my opinion.

That’s an interesting point. From a technical perspective it isn’t “the” ARM architecture. However, I strongly suspect that Castle wouldn’t complain if you used a different ARM architecture.

I’ve seen “Thumb” mentioned a few times but haven’t really followed it – is it also a different architecture and is it covered by the existing licence?

You want to see someone violate the terms of the licence?

Helps if you read both sentences together.

And understand how completely dependent RISC OS is on features of the ARM architecture.

Recall the difficulty of bringing Impression from 26 bit to 32 bit. Now consider adding “totally alien processor” into the mix and you’d realise that writing something original that resembles RISC OS in some vague way would be a lot less grief than even contemplating the idea of pouring it.

The only sensible way to get RISC OS onto an alien processor is…emulation. Fake an ARM and run it on that.

Recall the difficulty of bringing Impression from 26 bit to 32 bit. Now consider adding “totally alien processor” into the mix and you’d realise that writing something original that resembles RISC OS in some vague way would be a lot less grief than even contemplating the idea of pouring it.

What’s up? Just recompile, I mean it’s not like the source is a mass assembler code with some C mixed in is it? Oh…

The thing is that I’ve seen numerous posts about getting it all into C to make it easier to port to other processors¹ but then they diverge and talk about a non-ARM platform

BTW. “…pouring it” – I know it would be a bit of a fluid setup having something compatible but different, but “pouring”? ;P

¹ I’m sure ROOL, and anyone modifying RO would love the easy port aspect.

I love my MIST, but I don’t think it is useful beyond the “simulate some classic computers” field. The Archimedes core already pushes the MIST FPGA to its limits (although its author thinks that he can speed it up quite a bit), so implementing an ARMv7 core instead of the current ARMv2a core is probably off-limit.

In term of peripherals, we could imagine something better (new graphic modes, midi support, etc.), incompatible with RISC OS 3.1, but OK for RISC OS 5.

Of course there are much more powerful FPGAs available, but they get quite pricey quickly. And they would need to be perhaps 100x faster than the MIST’s FPGA to offer comparable speed to a 1 GHz Cortex-A9 or Cortex-A15.

Right, and no.
FPGA is the bridge to more classic offers (needs lot of money).

Also, implementing anything beyond ARMv2a or ARMv3 on a FPGA will wake up ARM’s “dogs of law” (pun), as more modern ARM architectures are heavyly guarded by patents and licences.

True. Would need to deliver evolution around ARM3, without making it a patented ARM :)
The result could be compatible with ARM3, with new things incompatible with newer ARM.

There are open components already available on OpenCores. MMU, DSP, FPU, GPU, Compression, CRC, Crypto, Jpeg…

BTW. “…pouring it” – I know it would be a bit of a fluid setup having something compatible but different, but “pouring”? ;P

What happens when your phone thinks it is smarter than you are. :-)

What happens when your phone thinks it is smarter than you are. :-)

Then it probably is. Mine has been dropped on it’s head too many times to believably claim that though.

The Aarch64 argument is an interesting one. The Pi3 has that but RISC OS runs in the 32 bit mode of the SoC. So really it comes to how “architecture” is defined, because a hypothetical 64 bit version of RISC OS would be running on the same die, using the same support circuitry and peripherals as 32 bit. Same architecture. Just utilising different features.

^{^} I can’t tell if you are joking.

Before anyone things Tristan has gone crazy and is talking to himself…. (a) he’s already crazy, (b) there was a spam post there which has now been deleted ;-)

I choose (a).

There was however a post which no longer exists.