Ticket #243 (Fixed)Sun Mar 28 17:38:42 UTC 2010

objasm 3.32 (and above?) accepts "MSR psr,rn,shift" as a legal instruction

Details by Jeffrey Lee (213):

objasm 3.32 allows the rn operand of an MSR instruction to receive a shift, even though no current version of the ARM architecture allows the MSR instruction to take a shifted register as input. E.g. “MSR CPSR_f, a2, LSL #28” is assembled without warning or error to the opcode &E128FE01, which the debugger module identifies as an undefined instruction, and when executed doesn’t appear to have the intended effect. Analysis of the ARMv7 ARM suggests that the CPU will treat it as opcode &E128F001, i.e. ignoring the shift.

This code has been in CVS for a few days now, and nobody has complained about it producing an error yet, so this bug probably still exists in the current version of objasm.