Ticket #423 (Fixed)Fri Apr 22 12:48:27 UTC 2016
Load/store exclusive handling is incomplete
| Reported by: | Jeffrey Lee (213) | Severity: | Normal |
| Part: | RISC OS: General | Release: | |
| Milestone: | Status | Fixed |
Details by Jeffrey Lee (213):
1. The OS needs to issue CLREX at certain points in order to be compliant with the LDREX/STREX usage rules laid out in the ARM ARM
2. synclib’s atomic_process_smp function needs rewriting to avoid making the process function call in the middle of the LDREX/STREX sequence
Failing to do either of these may result in unpredictable or undesirable behaviour, especially as we start to make more and more use of the exclusive access instructions.
Relevant forum thread:
Changelog:
Modified by Jeffrey Lee (213) Sun, May 08 2016 - 19:03:54 GMT
Part 2 should now be dealt with.
Modified by Jeffrey Lee (213) Wed, July 13 2016 - 12:58:30 GMT
- Status changed from Open to Fixed
Part 1 should now be dealt with as well
https://www.riscosopen.org/viewer/revisions/log…
https://www.riscosopen.org/viewer/revisions/log…
https://www.riscosopen.org/viewer/revisions/log…
https://www.riscosopen.org/viewer/revisions/log…
However, as noted in the kernel commit message, there are some situations where third-party code must issue CLREX itself in order to ensure ARM’s rules are followed: Non-transient callback handlers, custom abort handlers, FIQ handlers, and anything else which returns directly to interrupted user code is responsible for issuing its own CLREX if the code has done something that could have left the local monitor in the exclusive state (e.g. calling a SWI counts towards this, as there’s no guarantee the monitor will be open on exit from the SWI)
Some details about this have been added to the wiki, e.g. https://www.riscosopen.org/wiki/documentation/s…
