The release in 2011 of architecture ARMv8 added a whole new instruction set called AArch64 with wider 64b register bank, and renamed what was previously referred to as the ARM instruction set (which RISC OS uses) as AArch32. The AArch64 instructions are not binary compatible with the older ones.
To date, the ARMv8 targets RISC OS supports have been fortunate in still containing an implementation of AArch32 for backwards compatibility, allowing it to run and entirely ignoring the AArch64 aspects. As at 2020 it was becoming clear that Arm intended to wind down ARMv7 and earlier (fewer than 50% of the cores available to license would run that way) to focus on their ARMv8 offerings, of which many dropped AArch32 support entirely.
In April 2021 the ARMv9 architecture was announced with AArch32 relegated to being a license option, in much the same way that 26 bit mode became an option in ARMv4 rarely taken up.
This proposal identifies aspects of RISC OS that will require attention in order to migrate away from AArch32, to help making design decisions, and ultimately a route to implementing changes to ensure there are chips in future to run on.
The AArch32 is the family of instructions with 32 bit wide integer registers addressing up to 2 32 bytes of memory, and also includes the 26 bit addressing mode too.
The AArch64 is the family of instructions with 64 bit wide integer registers addressing up to 2 64 bytes of memory.
Assuming a register widening solution is adopted, the only places where the size of a pointer is of concern is where the pointer is passed in via a parameter block held in memory. This section surveys the core module SWIs for places where this technique is used in order to see how widespread a problem it might be.
OS_Word 0 (Read line)
OS_Word 16? (Econet transmit)
OS_Word 17? (Econet open or receive)
OS_Word 21 (Define pointer shape)
OS_Word 22 (Write screen base address)
OS_FSControl 26 (Copy objects)
OS_ChangeEnvironment handler 6 (Error handler)
OS_ChangeEnvironment handler 7 (Callback handler)
OS_ChangeEnvironment handler 8 (BreakPoint handler)
OS_DelinkApplication and OS_RelinkApplication
OS_HeapSort[32]
OS_ReadMemMapEntries and OS_SetMemMapEntries and OS_FindMemMapEntries
OS_Memory 0 (General page block operations)
Immediate operation Econet_JSR branches to a 32b address received via Econet, optionally to AArch32 code that follows it in the immediate buffer.
Wimp_Poll 13 (Pollword non-zero)
Wimp icon blocks include 32b pointers to sprite areas or validation strings overloaded with the 12 byte icon data.
Wimp menu blocks can include a 32b pointer to a submenu at offset +4 of the menu item data.
Podule_ReadInfo?
FileCore_MiscOp 6 (Read processed FileCore_Create block)
FileCore_DiscOp[64]
Draw path block code 1 is a 32b continuation path block pointer. There are plenty of spare code numbers to assign a new one for 64b pointers.
RemotePrinterSupport_EnumerateUSBPrinters?
The following list modules which have been checked but whose SWIs don’t have any potential pointer issues. Modules which don’t implement any SWIs, such as application modules, are not listed here.
The SWIs OS_File and OS_GBPB include some subreasons which deal with load and execution addresses. These are currently 32b quantities, albeit deprecated in use. Various places store these as 32b quantities for example: in the extended attributes of a ZIP file, in file server messages, in the directory entries of FileCore discs.
The SWI OS_FSControl 12 (Add FS) and OS_FSControl 35 (Add image FS) pass a pointer to a FileSwitch FS Information Block which includes 32b offsets to functions to implement a filing system. Provided modules are not expanded beyond their existing maximum size of 64MB these 32b offsets will suffice because they are relative to the module base address.
The SWI OS_SpriteOp doesn’t make use of absolute addresses in memory. Provided sprites are not expanded beyond their existing maximum size of 2GB these 32b offsets will suffice because they are relative to the sprite area base.
Podule loaders have 4xAArch32 instructions and an optional “32OK” signature at the start. Since AArch64 instructions are also 32b in size, and the signature could be changed, should there be an ARMv8+ machine with a podule bus, this can be accommodated.
The 4 word MessageTrans block is opaque to the caller, so while it may contain a pointer, its layout could be changed without impacting clients.
The SWI ResourceFS_RegisterFiles includes a block with a 32b offset to the next item to add in the chain, however that still allows blocks to be kept ±2GB apart.
Devices registered via the list in R1 to DeviceFS_Register include a 32b offset to the device name as the first word of the buffer. This limits the string to be within ±2GB of the block.
Toolbox Res files include 32b offsets (to the body, strings, etc) some of which are relocated when the Res file is loaded into absolute addresses.
v1.00 – 10-Apr-2021