Added the following code generation and optimisation options: -arch 6k, -arch 6t2, -arch 7 and -cpu cortex-a8. When -arch 7 or -cpu cortex-a8 is specified, then a new set of scheduling rules are selected which target an approximation of the Cortex-A8.
Multiple bugfixes:
Code generation improvement: unaligned halfword loads/stores fabricated from LDRB/STRB instructions can access larger offsets from the base register than LDRH/STRH instructions. However, this wasn’t being detected because the alignment field in the jopcode wasn’t being correctly initialised until too late.