Delete me: SDCard/Init (Rev #1)

Linux SDHCI driver init

Notes based on reading linux/drivers/mmc/host/sdhci.c

HC = Host Controller

sdhci_add_host

1. Reset the sdhci device (sdhci_reset)
2. Read the SDHCI_HOST_VERSION register (16 bit I/O) and mask out the version bits
3. If the Host Controller version >= 3.00, error that the controller version is unknown and may cause problems

1. If host→quirks contains SDHCI_QUIRK_MISSING_CAPS, return a faked up capabilities register, else caps⁰ = 32 bits of SDHCI_CAPABILITIES
2. If version >= 3.00, read SDHCI_CAPABILITIES_1 register and save in caps ¹, else save 0.

1. If host→quirks contains SDHCI_QUIRK_FORCE_DMA then

Controller quirks flags:

• Missing capabilities register (SDHCI_CAPABILITIES) – fake it up
• Force DMA (will use SDMA if available)
• DMA is broken (won’t use SDMA)
• ADMA is broken
• Base block frequency from capability reg is broken
• Data timeout uses SDCLK, so timeout= fmax / 1000
• Multiblock read ACMD12 available
• Force 1 bit data (see below)
• Broken card detection – so need to poll for card presence if card removable

If Host Controller 2.00 or later, will use ADMA if device can use it (capability bit SDHCI_CAN_DO_AMA2) and not disabled by quirk.

If no SDMA or ADMA, will fallback to PIO

If can do ADMA, allocate descriptors for scatter/gather entries – if can’t allocate fallback to SDMA.

Max clock freq (in MHz) is bits 15-8 in capability register in version >= 3.00, bits 13-8 before. (Check ‘CLOCK_BASE_BROKEN’ capability flag). Call host→ops→get_max_clock(host)

If HC >= 3.00, read out clock multiplier from caps ¹. If not supported or zero, clock multipler = 1

Calculate f_min and f_max:
f_max = max_clk
If spec 3.00 and clock multipler non-zero:
f_min = max_clk * clk_mul / 1024
f_max = max_clk * clk_mul
If spec 3.00 and clk_mul=0
f_min = max_clk / max clock divider from spec 3.00
If spec < 3.00
f_min = max_clk / max clock divider from spec 2.00

Read timeout clock from cap⁰. If zero, get from host→ops→get_timeout_clock if available. If caps⁰ SDHCI_TIMEOUT_CLK_UNIT bit set, time in ms else in seconds.

If spec 3.00 and can do ADMA or SDMA, then support command ACMD23, otherwise don’t.

Bus width:
Platform code (not sdhci.c) sets MMC_CAP_8_BIT_DATA if available on our board: controller may support it but have pins wired
If SDHCI_QUIRK_FORCE_1_BIT_DATA then we can use MMC_CAP_4_BIT_DATA

Speeds:
If spec >= 3.00 can use UHS-I mode (UHS_SDR12 and UHS_SDR25)
caps¹ says can support SDR104+SDR50 mode, or SDR50 mode
caps¹ says can support DDR50 mode
caps¹ says if need tuning for SDR50
caps¹ says if supports driver type A, type C, type D

Set power off notify timeout values (short or none)

Initialise re-tuning timer count from caps¹ (2^(caps_bits-1))

Tuning mode from caps¹

Read 32 bit SDHCI_MAX_CURRENT register

If can do VDD=3.3V (caps⁰), pick out max_current_330 from MAX_CURRENT register (in mA). If >150mA set XPC bit for 3.3V.

Same again for VDD=3.0V, 1.8V. Max current at 1.8V can be in steps of 800mA, 600mA, 400mA, 200mA.

ocr_avail section (something to do with available voltage ranges)