Entry | |
---|---|
- | - |
Exit | |
---|---|
R0 | Corrupt |
Any writebuffers are to be drained so that any pending writes are guaranteed completed to memory.
Although ARMv7 has DSB and DMB instructions which perform write buffer drain-style operations in a cache-agnostic manner, these instructions do not operate on caches which are not fully integrated with the CPU – e.g. the PL310 L2 cache that’s typically used on Cortex-A9 systems. Therefore, to ensure bufferable data is fully flushed to main memory, this ARMop must be used rather than a single ARMv7 sync instruction.