Delete me: CC 569 changes (Rev #2, changes)

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Added the following code generation and optimisation options: -arch 6k, -arch 6t2, -arch 7 and -cpu cortex-a8. When -arch 7 or -cpu cortex-a8 is specified, then a new set of scheduling rules are selected which target an approximation of the Cortex-A8.

Multiple bugfixes:

• Internal inconsistency error: CSE tried to simplify (register &~ register) where both register values were constants, but the code to evaluate the resultant J_BICK jopcode was missing.

• Internal inconsistency error in RTSupport module and elsewhere: ARM code generator was lacking handling of unaligned J_STRWK jopcode. When configured for no halfword store instructions, all halfword stores have been converted to byte stores in the machine independent part before reaching here, so this wasn’t noticed until ROM builds started to be done with halfwords enabled. New case inserted based on unaligned J_STRK code – if base is word aligned and offset is multiple of 2, proceed as for aligned store, else emit 2 STRBs and a shift. Uses ip as a temporary register – matching change to record this fact inserted in peepholer.

• Various failures where compile-time long long arithmetic is used: cse_scanblock loops over all the jopcodes in a block. It uses c, the pointer to the current instruction, and n, the instruction index, used for loop termination. If it finds a run-time compile-time evaluable long long support function, it can replace theCALL function and two preceding argument marshalling instructions with an ADCON and two LDRK jopcodes. Once it has done this, it needs to go back and rescan instructions from the ADCON onwards. However, it only updated c and not n, which means the last 3 or more instructions of the block don’t get CSE scanned. In the reported bug, this means the local store usage counts are incorrect and it incorrectly deduces that it can optimise away the support function entirely.

• Other miscalculations in compile-time long long arithmetic: if the resultant 64-bit quantity could be expressed as two 32-bit ARM immediate constants, then the conversion back into a 64-bit number in order to evaluate the result messed up, and bit 31 was sign-extended up to bit 63.

Code generation improvement: unaligned halfword loads/stores fabricated from LDRB/STRB instructions can access larger offsets from the base register than LDRH/STRH instructions. However, this wasn’t being detected because the alignment field in the jopcode wasn’t being correctly initialised until too late.