Multi-core RISC OS (Rev #2, changes)
Showing changes from revision #1 to #2:
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Placeholder page category: Specification
Goals
(Using more than 1 core, threading, SWI reentrancy, memory, interrupts)
Existing documentation
Relevant specifications
Relevant forum threads
Terminology
A term is a placeholder.
Detail
Implementation progress
| Phase | Status | Completion | Latest updates |
|---|---|---|---|
| Conceptual design | In progress | 0% | 26-Dec-2021 Document created |
| Mock ups/visualisation | - | - | - |
| Prototype coding | - | - | - |
| Final implementation | - | - | - |
| Testing/integration | - | - | - |
Document history
v1.00 – 26-Dec-2021
- Outline added
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