VFP Execution Environment (Rev #6, changes)

Showing changes from revision #5 to #6: Added | Removed | Changed

Goals

There is currently a bias towards using the older FPA instruction set for floating point operations ostensiby because the majority of RISC OS systems were based around the ARM7500FE or lacked floating point hardware entirely – and in that situation a floating point emulator was a good way to have code be able to run in either scenario.

Since ARM11 the scales have tipped the other way as these cores implement one variant or another of the VFP hardware macrocell, Arm’s replacement for the FPA. Ignoring VFPv1, since RISC OS never ran on any of the chips and version 1 has since been obsoleted, this means VFPv2 or VFPv3 or VFPv4.

To proposal looks at how to better integrate hardware floating point support within RISC OS, primarily for those clients of the Shared C Library, but also setting out examples by which hardware floating point support can be detected so that when multiple variants are supplied the correct one is run.

Existing documentation

Relevant specifications

Relevant forum threads

Terminology

FPA is the original Floating Point Accelerator, coprocessor numbers 1 & 2 for the ARM.
VFP is the Vector Floating Point unit, coprocessor numbers 10 & 11 for the ARM.
The APCS is the ARM Procedure Calling Standard, treated as a synonym here for ATPCS (for ARM/Thumb PCS), and AAPCS (for ARM Architecture PCS).
An ABI defines an Application Binary Interface, comprising a base ABI for the core-registers only and basis for several variants.

Detail

APCS amendments

The Shared C Library

Client registration

Code which is not a client of the Shared C Library)

Toolchain switches

Disc based components

ROM based components

VFP Emulator

NEON and the NeVer condition code

Why not retrofit FPEmulator?

Selecting a !RunImage

Implementation progress

Document history

v1.00 – 26-Dec-2021

• Outline added