IIC_Control
IIC
» SWI Calls
» IIC_Control
IIC_Control
(SWI &240)
| Entry | |
|---|---|
| R0 | Device address (bits 1-7), R/W flag (bit 0 set to read, clear to write) |
| R1 | Pointer to block |
| R2 | Size of block (number of bytes to transfer) |
| Exit | |
|---|---|
| R0-R2 | Corrupted |
Use
The purpose of this call is to allow software to perform transfers on the primary IIC bus that are present in the system.
There is no support for repeated start conditions, so for most simple transfers this SWI would be called twice – the first time to write a value (such as a register offset) and then to read one or more bytes of data from the device.
Errors
Possible errors are:
| &20300 | No acknowledge from IIC device |
| &20301 | IIC system busy / IIC operation in progress |
Notes
The benefit of IIC_Control is that it is simple to use. However, for more flexibility including support for multiple IIC buses and the ability to perform a complete interaction as an atomic transfer (via repeated start), please refer to OS_IICOp.
On older systems, IIC_Control disables interrupts during the actual transfer.
On newer systems (RISC OS 5), IIC_Control internally calls OS_IICOp.
See also
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