OS_Memory 64
OS SWI Calls
» OS_Memory
» OS_Memory 64
OS_Memory 64
(SWI &68)
| Entry | |
|---|---|
| R0 | 64, and flags, |
| R1 | Pointer to 64 bit page block list |
| R2 | Number of entries in page block list |
| Exit | |
|---|---|
| R0 | Preserved |
| R1 | Preserved |
| R2 | Preserved |
Use
The purpose of this call is to convert between different memory spaces used to specify addresses in a page block, and alter their cache-ability.
Notes
This call was introduced in RISC OS 5.29, and is an extended form of OS_Memory 0, to allow full interaction with pages which have logical or physical addresses which can’t be represented in the 32 bit page block format. I.e. pages with physical addresses >= 2^32 (possible on ARMv7+ machines which support the Large Physical Address Extension), or pages with logical addresses >= 2^32 (for future AArch64 versions of RISC OS). For AArch32 versions of RISC OS, your code can decide whether to use OS_Memory 0 or OS_Memory 64 by checking bit 21 of OS_PlatformFeatures 0.
The addresses must be in RAM; specifically, they must all correspond to pages which the OS has assigned a valid physical page number to. E.g. I/O memory which has been mapped by OS_Memory 13 will not be recognised.
Addresses need not be page aligned. If a page is made uncacheable, the relevant portion of the CPU cache will be flushed. If there is an error processing any page in the block, the call has no effect on any pages.
See also
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