Address Exception Handler (changes)

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OS SWI Calls

» OS_ChangeEnvironment

» Address Exception Handler

Address Exception Handler

The address exception handler is entered in the following state:

• The processor will be in SVC26 mode, with IRQs disabled
• FIQ state will match that at the time of the exception
• R14 will contain the exception address and saved PSR, corresponding to when the exception was raised by the CPU. R14 will be pointing two instructions (i.e. 8 bytes) after the instruction that caused the exception.
• The other core registers will be as per when the exception was raised by the CPU. However if your code examines the registers it must take care to use the correct register bank (e.g. if the exception was from user mode, it should look at R14_usr, not R14_svc).
• R13 will be a valid stack pointer

If the handler is capable of handling the exception (e.g. by emulating the memory access) then it can resume execution by performing a suitable exception return operation.

Notes

Address exceptions are only capable of being generated on MEMC-based hardware; on RISC OS 3.5 and later this environment handler is unused.

The kernel’s default handler will save a copy of the ARM integer registers (corresponding to the CPU mode the exception occurred in) to the Exception Registers Block, reset the stack pointers for all the privileged CPU modes, and then call OS_GenerateError to report an Address Exception error.

See also

• OS_ChangeEnvironment