Archimedes Hardware (changes)

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Programmer's Reference Manuals

» Part 1 - Introduction?ARM Hardware

» Archimedes – Legacy Hardware 1ARM Hardware

Overview

This section details the intricacies of the early hardware used by RISC OS. A number of different models of RISC OS computers are classified as Archimedes. Each Archimedes model of computer had an ARM 2 or ARM 3 as the CPU. Several different chips supported the ARM processor. These chips were designed by Acorn Computers Ltd, and were proprietary chips.

RISC OS 2 and RISC OS 3.11 were used with this class of hardware. The information is no longer valid or useful with RISC OS 5, but is available here for completeness.

Chips

The list of chips used within the original Acorn Archimedes range of computers is as follows:

1. ARM processor is the CPU
2. VIDC chip which handled both video and sound output. VIDC is short for Video Controller
3. IOC chip handles the peripherals and interrupts. IOC is short for Input/Output Controller
4. MEMC chip is used as the interface between the ARM, VIDC and IOC and memory. MEMC is short for Memory Controller

ARM Processor

The ARM processor ships used with the Archimedes range of computers were the ARM 2 and ARM 3 which are based on the ARM v2(as) architecture. Newer versions of processors introduced new processor modes, and other important features.

An important limitation of the ARM v2(as) architecture is it’s 26-bit address. This results in only 64 MB of addressable memory (2^26^ = 64 MB). The address bus was 26-bits in size because R15 used to store the address, was also used to store the status register.

Word Size

The ARM range of processors uses 32-bit words. Each instruction fits into a single word. It also has a 32-bit data bus so that complete instructions can be fetched in a single step.

Processor Modes

ARM 2 and ARM 3 processors can operate in four different modes. They are as follows:

Supervisor Mode, Interrupt Mode and Fast Interrupt Mode are all privileged modes that allow extra control over the computer.

Changing Processor Mode

If the ARM processor is forced to change mode, you must follow this with a no-op command. This is to avoid contention, by allowing the processor time to complete writing to the registers, before switching to the other mode.

Overview of Registers

Twenty seven 32-bit registers are available on the ARM 2 and ARM 3 processor. Of those, only 16 are available within RISC OS. Some registers are shared across different modes, while others are not. The table below shows this:

Two registers have special functions. They are:

• R15 is used as the Program Counter (PC_) and the Processor Status Register (_PSR)
• R14 (R14_svc, R14_R14_irq and R14_fiq) are used as subroutine link registers

In addition, RISC OS has a convention of using R13 (R13_svc and R13_irq) as private stack pointers for each Processor Mode.

All other registers are deemed as general purpose.

R15 – Program Counter and Processor Status Register

As mentioned above, R15 is used as the Program Counter (PC_) and the Processor Status Register (_PSR). 24-bits is used for the PC, and 8-bits for the PSR.

The contents of R15 is as follows:

¹ The Processor Mode Flags are not stored in R15, but simply appended to the Program Counter when fetching instructions, thus forming a 26-bit address. The Program Counter must always be word-aligned, and the bottom two bits of the address must always be zero.

R14 – Subroutine Link Registers

R14 (R14_svc, R14_R14_irq and R14_fiq) are used as subroutine link registers. R14 receives a copy of the PC and PSR when a Branch and Link instruction is executed. R14_svc, R14_R14_irq and R14_fiq are used to store the values of R15 when any of the following events occur:

• Interrupts and exceptions arise
• Branch and Link instructions are executed in Supervisor or interrupt routines
• When a SWI instruction is used

R13 – Private Stack Pointers

RISC OS has a convention of using R13 (R13_svc and R13_irq) as private stack pointers for each Processor Mode.

Any routines written that are called from User Mode, but run in SVC or IRQ mode will need to use some of the shared register R0 to R12. Therefore, you must preserve the registers on a stack before you later the registers, and subsequently restore them before returning from your routine.

SVC and IRQ Mode stacks must b full descending stacks and ending at a megabyte boundary. System stack locations should not be changed, however, if they are changed, please note that they are reset to their default locations when errors are generated, and when applications are started.

Routine in FIQ mode require a faster response, so there are seven private registers in FIQ Mode. These should be enough registers to avoid the overhead of having to save them to a stack and using the shared registers. However, if you need to do so, you should use R13_fiq as the stack pointer.

You can use R13 and/or R13_fiq as conventional registers is they are not used as stack pointers.

The VIDC chip

The VIDC chip controls the computer’s video and sound. The data is read from RAM into buffers and then processed and converted into the necessary analogue signals to drive the video output displays and sound system. The VIDC can handle many different display and sound formats.

There are three buffers for input data. They are:

1. Video data
2. Sound data
3. Cursor data

Each buffer is of the type FIFO (first-in, first-out). Data is requested in blocks of four 32-bit words at a time. The MEMC chip controls the addressing and fetching of the data under DMA (Direct Memory Access) control.

Video

Data from the video buffer is converted and processed. The are as follows:

1. Data is serialised by the VIDC chip into either 1, 2, 4 or 8 bits per pixel
2. Passed through a colour look-up palette (16 registers, each is 13-bits wide resulting in 4096 possible colours)
3. The output is then converted by three 4-bit digital to analogue converters (DACs). One for red, green and blue colour
4. Output is then used to drive the display output device

The registers that control the video system provide a wide range of options. They are as follows:

• Pixel rate can be selected as 1/3, 1/2, 2/3 or 1 times the clock rate of the VIDC chip¹
• Horizontal timing can be controlled (in units of 2 pixels)
• Vertical timing can be controlled (in units of a raster)
• Width of screen border can be altered
• Screen border can be set to any of the 4,096 possible colours
• Interlaced displays
• External synchronisation
• Very high resolution monochrome screen modes (up to 96 MHz pixel rate)

¹ Different versions of the VIDC chip can handle different clock speeds. The original version was 24 MHz, whereas the newer versions could be 25.175 or 36 MHz.

Sound

Up to eight separate channels of mono sounds is provided by the VIDC chip. Each channel can be assigned a stereo position (between left to right) by the use of eight stereo image registers.

Data from the buffer is converted and processed. The following steps taken:

1. Data from the buffer is read at a programmable rate
2. Data is then passed to an 8-bit DAC
3. DAC uses the stereo image registers to convert the digital samples to a stereo analogue sample
4. It is then sent to the computer’s internal amplifier

Cursor

The cursor data controls a pointer than can be up to 32 pixels wide, and an unlimited number of rasters high, although RISC OS restricts this to a maximum of 32 rasters in height. The pixels can be transparent or can be any of three of the 4,096 possible colours.

The cursor may be positioned anywhere on the screen (within the border).

The IOC chip

The IOC chip manages the peripherals and interrupts throughout the computer. It controls a data bus that peripherals are connected to. In addition, it also provides numerous internal functions that are accessed without any wait states, and a flexible control port.

Peripheral support

The IOC communicates to the rest of the system via the high speed system bus. It is able to handle different speeds of data transfers via the Input/Output or expansion bus automatically.

The specification of the IOC chip is as follows:

• Sixteen interrupt inputs (14 level sensitive and 2 edge-triggered)
• Seven external peripheral select outputs
• Four programmable peripheral timing cycles (slow, medium, fast and 2 MHz
  synchronous)

RISC OS views the IOC and peripherals as memory-mapped devices. Most peripherals are byte-wide, and word aligned. A single memory instruction can be used to perform any of the following:

• Access IOC control registers
• Select both a peripheral and timing cycle it requires, and access it

A wide range of peripherals are supported by the IOC chip including those that require an interruptible I/O cycle.

Internal functions

The following functions are provided by the IOC chip:

• Full-duplex, bidirectional serial keyboard interface
• Interrupt mask, request and status registers for both normal and fast interrupts
• Six programmable bidirectional control pins
• Four independent 16-bit programmable counters. Two are used as baud rate generators (keyboard and serial port). The third counter (Timer 0_) is used to generate system timing events. The last counter (_Timer 1) is unused by RISC OS, and can be used freely by developers

The MEMC chip

The MEMC chip is used as the interface between the ARM, VIDC and IOC and memory. A single clock input provides all the timing signals by the ARM chip set.

Memory Support

It provides the control signals needed by memory of different speed. The specifications are as follows:

• Provides timing and refresh signals for DRAM
• Provides control signals for several access times of ROM.
  **The timings are 200ns, 325ns and 450ns when the MEMC is clocked at 8 MHz
  • The timings are lower (in inverse proportion) when the MEMC is clocked at 10 or 12 MHz
• Can handle up to 32 standard DRAMs can be driven (4 MB of real memory using 1 Mbit devices)
• Can access fast page DRAM to maximise memory bandwidth

Memory Mapping

The MEMC chip maps the physical memory into a 16 MB slot, with the base address at 32 MB. RISC OS does not address this slot directly; instead it addresses another 32 MB logical slot within the 64 MB logical address space.

Each page of the slot that RISC OS addresses can be:

• Unmapped
• Mapped onto one page of physical memory
• Mapped onto numerous pages of physical memory

RISC OS can only read and write from pages that have one-to-one mappings. One-to-many mappings is used to hide pages of applications away when several applications are sharing the same address within the window environment. These addresses start from &8000 upwards, although of course, the pages are not held at &8000.

The physical memory is divided into physical pages. The 32 MB of logical space is divided into logical pages of the same size. The logical page is mapped to the physical page, and the MEMC keeps track of this.

Page size

The MEMC chip has 128 pages to use for its memory mapping. Each page is used to translate a logical address to a physical address. This is achieved by using a content-addressable memory (CAM). Most Archimedes machines use the full 128 pages, but some like the Archimedes 305 only uses 64 pages.

If the MEMC chip does use 128 pages, or any constant number, then:

• The allocated size of each page increases as the computer’s physical memory increases. This is because the large amount of memory is being divided into the same number of pages
• The number of logical pages decrease as the size of each page increases. This is because the amount of physical memory is being divided into larger pages

The maximum amount of memory that a single MEMC chip can access is 4MB. If more memory is required, more MEMC chips must be added (in a master > slave scenario).

The table below provides an example of a ‘typical’ Archimedes computer and it’s page sizes. The values are only provided for guidance, and must not be relied upon across the whole Archimedes range of computers.

To read the computer’s page size, you may use the OS_ReadMemMapInfo SWI.

RISC OS programs a minimum of 128 pages, even though it may not use them all. The reasons for this are:

• Random hits in unused pages do not happen
• Extra MEMC chips can be added as slaves to the master MEMC chip allowing for more than 4MB of physical memory to be accessed

Protection Levels & Protection Modes

There are three different protection modes are available to the MEMC chip:

• Supervisor
• Operating System
• User

Each page of memory is set at one of three different protection levels:

• Protection level 0
• Protection level 1
• Protection level 2 (there is a level 3, but it is identical to level 2)

The protection level in conjunction with the protection mode, specifies whether read and/or write access to a page of memory is allowed. This is determined as follows:

Any attempt to access protected memory from an insufficient protection mode, results in the MEMC trapping the exception and sending an abort signal to the ARM processor.

Memory

The table below show the memory map of a RISC OS Archimedes computer.

IMAGE GOES HERE (UPDATED WIKI REQUIRED)

DMA support

The MEMC chip also provides three programmable address generators to support Direct Memory Access (DMA). They are used for:

• Double buffers for sound data
• Linear buffer for cursor sprite
• Circular buffer for video refresh

See also

• OS_ReadMemMapInfo