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HAL boot process

IOMD-based machines (Risc PC, A7000, A7000+, NCs)

Booting starts in castle/RiscOS/Sources/HAL/IOMD/s/Attic/Boot apache/RiscOS/Sources/HAL/IOMD/s/Attic/Boot

This contains the reset vectors. The OS will boot either from a 32 bit ROM with 32 bit reads, or a 16 bit ROM with a 16 bit reads. If a 32 bit ROM is used but IOMD is reading 16 bit words, the reset vectors will read as NV-condition instructions and drop through to some 16 bit wide instructions designed to force IOMD to use a 32 bit databus.

start is the first code called. It assumes the RISC OS image may be found 64KiB above the reset vectors (HAL_Base).

Some careful initialisation of hardware is required, for separate cases of ARM7500, ARM7500FE and other ARMs.

On ARM7500FE (init7500FEcpu) and ARM75000 (init7500cpu) we set up different memory timings. StrongARM 110 (MedusaInit) we enable the fast core clock. On all machines we set up timing for different areas of hardware by setting IOMD.

Now we call CommonInit. First we initialise the VIDC. Everything but keyboard interrupts off. Set up IOMD timer 0. Some code to help the ARM7500/ARM7500FE’s VIDC voltage controller oscillator (used to produce video timing) to start up – apparently it can be a little sticky.

Here the HAL looks like it’s hardcoded to a 16MB RAM bank &10000000 – &11000000 and ROM image at &10B00000-&10F00000

Lastly we check the CMOS protection link.

Now we indirect to kernel entrypoint OS_Start to call the OS proper.

Iyonix hardware

Boot code may be found in castle/RiscOS/Sources/HAL/Tungsten/s/Top apache/RiscOS/Sources/HAL/Tungsten/s/Top

We call start then restart. This code assumes we’re on an XScale. We turn off MMU and cache, invalidate cache and TLB. Again we assume the RISC OS ROM image lives 64KiB above the reset vectors.

We set up the CPU mode (no write buffer, 32 bit data and program space). Make sure we’re in SVC32 mode.

Next we call initialise_rom which sets up the PBI bus to access the 16-bit-wide flash device, and sets up flash timing.

We also initialise_iic – setting the GPIO registers that drive the bus.

Now we initialise_ram (HAL/Tungsten/s/RAM). Here we set up the DDR SDRAM timing (this RAM setup, and the flash recovery code must be in the first 8KiB of RAM – because it’s within the first write protected flash sector). The Application Accelerator is used to zero the entire RAM.

Back in the restart routine (HAL/Tungsten/s/Top) we now have a stack. Now we can make a RAM copy of the ROM. There’s code to use the Application Accelerator, but by default it’s done in a loop and a checksum kept.

We invalidate the instruction cache and jump into the RAM copy. Again we invalidate the I-cache and reprogram the ROM out of the processor vector space (replaced by RAM holding the soft-copy of the OS)

Here if flag FlashCheck is set we test the checksum, and if it fails flash the floppy drive light and request a new ROM image down the serial port.

All being well we call rom_checkedout_ok (HAL/Tungsten/s/Boot). The OS is notified of the existing RAM bank via OS_AddRAM (which goes across the HAL interface to the OS – see RISCOS_AddRAM in Kernel/s/HAL).

Finally we indirect to OS_Start to start the OS.

Kernel boot

RISCOS_Start is in castle/RiscOS/Sources/Kernel/s/HAL apache/RiscOS/Sources/Kernel/s/HAL.