Showing changes from revision #0 to #1:
Added | Removed | Changed
Entry | |
---|---|
R0 | Logical address of start of range (inclusive, cache line aligned) |
R1 | Logical address of end of range (exclusive, cache line aligned) |
Exit | |
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R0 | Corrupt |
The cache or caches are to be invalidated for the specified address range, with cleaning of any writeback data being properly performed.
Note that any write buffer draining should also be performed by this operation, so that memory is fully updated with respect to any writeback data.
The OS only expects the invalidation to be with respect to instructions/data that are not involved in any currently active interrupts.