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Added | Removed | Changed
Entry | |
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R0 | Flags: |
Bit 0: 1=start next queued transfer, 0=do not start queued transfers | |
Bits 1-31: Reserved (set to 0) | |
R1 | DMA tag |
Exit | |
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- | All registers preserved |
This SWI is used to suspend the given active DMA transfer.
The suspension of a transfer is achieved by the following steps:
If bit 0 of R0 is clear then no DMA requests for the same logical channel will be started until the suspended transfer is resumed or terminated.
An error block is returned if the DMA tag is invalid, or the specified DMA transfer is not in progress.
This documentation only covers the RISC OS 5 version of the DMAManager SWIs. For other OS versions, consult the appropriate PRM volume (e.g. volume 5a).