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Although this call doesn’t guarantee that any memory operation completes, it’s usually all that’s required when interacting with hardware devices which use memory-mapped IO. E.g. after reading a hardware register to detect that a DMA write to RAM has completed, issue a read barrier to ensure that any reads from the data buffer see the final data.
There is no direct equivalent to this in ARMv7 (barriers are either W or RW). However it’s useful to define a read barrier, as (e.g.) on Cortex-A9 a RW barrier would require draining the write buffer of the external PL310 cache, while a R barrier can simply be an ordinary DMB instruction.