DMB_ReadWrite ARMop (changes)

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» DMB_ReadWrite ARMop

DMB_ReadWrite ARMop

Use

This call is roughly equivalent to the ARMv7 “DMB SY” instruction:

• Ensures in-order operation of data load/store instructions
• Does not stall instruction execution
• Does not guarantee that any preceeding memory operations complete in a timely manner (or at all)

Notes

Although this call doesn’t guarantee that any memory operation completes, it’s usually all that’s required when interacting with hardware devices which use memory-mapped IO. E.g. fill a buffer with data, issue a DMB, then write to a hardware register to start some external DMA. The writes to the buffer will have been guaranteed to complete by the time the write to the hardware register completes.

Although ARMv7 has DSB and DMB instructions which perform write buffer drain-style operations in a cache-agnostic manner, these instructions do not operate on caches which are not fully integrated with the CPU – e.g. the PL310 L2 cache that’s typically used on Cortex-A9 systems. Therefore, to get a barrier that ensures the correct ordering of memory accesses across all levels of the cache/memory hierarchy, the memory barrier ARMops must be used rather than a direct ARMv7 barrier instruction.

See also

• OS_MMUControl 2