DSB_Write ARMop (changes)

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» DSB_Write ARMop

DSB_Write ARMop

Use

This call is roughly equivalent to the ARMv7 “DSB ST” instruction:

• Writebuffers are drained
• Write barrier – reads may cross the instruction
• Instructions following the barrier will only begin execution once the barrier is passed – but any prefetched instructions are not flushed from the pipeline

Notes

Although ARMv7 has DSB and DMB instructions which perform write buffer drain-style operations in a cache-agnostic manner, these instructions do not operate on caches which are not fully integrated with the CPU – e.g. the PL310 L2 cache that’s typically used on Cortex-A9 systems. Therefore, to ensure bufferable data is fully flushed to main memory, the memory barrier ARMops must be used rather than a direct ARMv7 sync instruction.

See also

• OS_MMUControl 2